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[174.21.71.127]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-aab358fc6d8sm5788145a12.51.2025.01.21.07.47.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jan 2025 07:47:13 -0800 (PST) Message-ID: Date: Tue, 21 Jan 2025 07:47:10 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] target/riscv: throw debug exception before page fault To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com References: <20250120204910.1317013-1-dbarboza@ventanamicro.com> <20250120204910.1317013-3-dbarboza@ventanamicro.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250120204910.1317013-3-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/20/25 12:49, Daniel Henrique Barboza wrote: > In the RISC-V privileged ISA section 3.1.15 table 15, it is determined > that a debug exception that is triggered from a load/store has a higher > priority than a possible fault that this access might trigger. > > This is not the case ATM as shown in [1]. Adding a breakpoint in an > address that deliberately will fault is causing a load page fault > instead of a debug exception. The reason is that we're throwing in the > page fault as soon as the fault occurs (end of riscv_cpu_tlb_fill(), > raise_mmu_exception()), not allowing the installed watchpoints to > trigger. > > Call cpu_check_watchpoint() in the page fault path to search and execute > any watchpoints that might exist for the address, never returning back > to the fault path. If no watchpoints are found cpu_check_watchpoint() > will return and we'll fall-through the regular path to > raise_mmu_exception(). > > [1] https://gitlab.com/qemu-project/qemu/-/issues/2627 > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2627 > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu_helper.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index e1dfc4ecbf..ae0a659ec7 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -27,6 +27,7 @@ > #include "exec/page-protection.h" > #include "instmap.h" > #include "tcg/tcg-op.h" > +#include "hw/core/tcg-cpu-ops.h" > #include "trace.h" > #include "semihosting/common-semi.h" > #include "system/cpu-timers.h" > @@ -1708,6 +1709,24 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > } else if (probe) { > return false; > } else { > + int wp_len = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; Surely 'size' may be relevant? r~ > + int wp_access = 0; > + > + if (access_type == MMU_DATA_LOAD) { > + wp_access |= BP_MEM_READ; > + } else if (access_type == MMU_DATA_STORE) { > + wp_access |= BP_MEM_WRITE; > + } > + > + /* > + * If a watchpoint isn't found for 'addr' this will > + * be a no-op and we'll resume the mmu_exception path. > + * Otherwise we'll throw a debug exception and execution > + * will continue elsewhere. > + */ > + cpu_check_watchpoint(cs, address, wp_len, MEMTXATTRS_UNSPECIFIED, > + wp_access, retaddr); > + > raise_mmu_exception(env, address, access_type, pmp_violation, > first_stage_error, two_stage_lookup, > two_stage_indirect_error);