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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a892e5f44dsm2482871f8f.87.2025.06.27.04.54.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jun 2025 04:54:23 -0700 (PDT) Message-ID: Date: Fri, 27 Jun 2025 13:54:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 02/11] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, imammedo@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, gustavo.romero@linaro.org, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250623094230.76084-1-shameerali.kolothum.thodi@huawei.com> <20250623094230.76084-3-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250623094230.76084-3-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/23/25 11:42 AM, Shameer Kolothum wrote: > Introduce a new struct AcpiIortSMMUv3Dev to hold all the information > required for SMMUv3 IORT node and use that for populating the node. > > The current machine wide SMMUv3 is named as legacy SMMUv3 as we will > soon add support for user-creatable SMMUv3 devices. These changes will > be useful to have common code paths when we add that support. > > Tested-by: Nathan Chen > Reviewed-by: Nicolin Chen > Reviewed-by: Jonathan Cameron > Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger > --- > hw/arm/virt-acpi-build.c | 109 +++++++++++++++++++++++++++------------ > hw/arm/virt.c | 1 + > include/hw/arm/virt.h | 1 + > 3 files changed, 77 insertions(+), 34 deletions(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 7e8e0f0298..28489cf59f 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -266,6 +266,34 @@ static int iort_idmap_compare(gconstpointer a, gconstpointer b) > return idmap_a->input_base - idmap_b->input_base; > } > > +typedef struct AcpiIortSMMUv3Dev { > + int irq; > + hwaddr base; > + GArray *idmaps; > + /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ > + size_t offset; > +} AcpiIortSMMUv3Dev; > + > +static void populate_smmuv3_legacy_dev(GArray *sdev_blob) > +{ > + VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine()); > + AcpiIortSMMUv3Dev sdev; > + > + sdev.idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); > + object_child_foreach_recursive(object_get_root(), iort_host_bridges, > + sdev.idmaps); > + /* > + * There can be only one legacy SMMUv3("iommu=smmuv3") as it is a machine > + * wide one. Since it may cover multiple PCIe RCs(based on "bypass_iommu" > + * property), may have multiple SMMUv3 idmaps. Sort it by input_base. > + */ > + g_array_sort(sdev.idmaps, iort_idmap_compare); > + > + sdev.base = vms->memmap[VIRT_SMMU].base; > + sdev.irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; > + g_array_append_val(sdev_blob, sdev); > +} > + > /* > * Input Output Remapping Table (IORT) > * Conforms to "IO Remapping Table System Software on ARM Platforms", > @@ -274,11 +302,12 @@ static int iort_idmap_compare(gconstpointer a, gconstpointer b) > static void > build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > { > - int i, nb_nodes, rc_mapping_count; > - size_t node_size, smmu_offset = 0; > - AcpiIortIdMapping *idmap; > + int i, j, nb_nodes, rc_mapping_count; > + AcpiIortSMMUv3Dev *sdev; > + size_t node_size; > + int num_smmus = 0; > uint32_t id = 0; > - GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); > + GArray *smmuv3_devs = g_array_new(false, true, sizeof(AcpiIortSMMUv3Dev)); > GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); > > AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, > @@ -286,28 +315,32 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > /* Table 2 The IORT */ > acpi_table_begin(&table, table_data); > > - if (vms->iommu == VIRT_IOMMU_SMMUV3) { > - AcpiIortIdMapping next_range = {0}; > - > - object_child_foreach_recursive(object_get_root(), > - iort_host_bridges, smmu_idmaps); > - > - /* Sort the smmu idmap by input_base */ > - g_array_sort(smmu_idmaps, iort_idmap_compare); > + nb_nodes = 2; /* RC, ITS */ > + if (vms->legacy_smmuv3_present) { > + populate_smmuv3_legacy_dev(smmuv3_devs); > + } > > + num_smmus = smmuv3_devs->len; > + if (num_smmus) { > + AcpiIortIdMapping next_range = {0}; > + int smmu_map_cnt = 0; > /* > * Split the whole RIDs by mapping from RC to SMMU, > * build the ID mapping from RC to ITS directly. > */ > - for (i = 0; i < smmu_idmaps->len; i++) { > - idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); > - > - if (next_range.input_base < idmap->input_base) { > - next_range.id_count = idmap->input_base - next_range.input_base; > - g_array_append_val(its_idmaps, next_range); > + for (i = 0; i < num_smmus; i++) { > + sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); > + for (j = 0; j < sdev->idmaps->len; j++) { > + AcpiIortIdMapping *idmap = &g_array_index(sdev->idmaps, > + AcpiIortIdMapping, j); > + if (next_range.input_base < idmap->input_base) { > + next_range.id_count = idmap->input_base - > + next_range.input_base; > + g_array_append_val(its_idmaps, next_range); > + } > + next_range.input_base = idmap->input_base + idmap->id_count; > + smmu_map_cnt++; > } > - > - next_range.input_base = idmap->input_base + idmap->id_count; > } > > /* Append the last RC -> ITS ID mapping */ > @@ -316,10 +349,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > g_array_append_val(its_idmaps, next_range); > } > > - nb_nodes = 3; /* RC, ITS, SMMUv3 */ > - rc_mapping_count = smmu_idmaps->len + its_idmaps->len; > + nb_nodes += num_smmus; > + rc_mapping_count = smmu_map_cnt + its_idmaps->len; > } else { > - nb_nodes = 2; /* RC, ITS */ > rc_mapping_count = 1; > } > /* Number of IORT Nodes */ > @@ -341,10 +373,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > /* GIC ITS Identifier Array */ > build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); > > - if (vms->iommu == VIRT_IOMMU_SMMUV3) { > - int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; > + for (i = 0; i < num_smmus; i++) { > + sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); > + int irq = sdev->irq; > > - smmu_offset = table_data->len - table.table_offset; > + sdev->offset = table_data->len - table.table_offset; > /* Table 9 SMMUv3 Format */ > build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ > node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; > @@ -355,7 +388,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > /* Reference to ID Array */ > build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); > /* Base address */ > - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); > + build_append_int_noprefix(table_data, sdev->base, 8); > /* Flags */ > build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); > build_append_int_noprefix(table_data, 0, 4); /* Reserved */ > @@ -404,15 +437,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > build_append_int_noprefix(table_data, 0, 3); /* Reserved */ > > /* Output Reference */ > - if (vms->iommu == VIRT_IOMMU_SMMUV3) { > + if (num_smmus) { > AcpiIortIdMapping *range; > > /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ > - for (i = 0; i < smmu_idmaps->len; i++) { > - range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); > - /* output IORT node is the smmuv3 node */ > - build_iort_id_mapping(table_data, range->input_base, > - range->id_count, smmu_offset); > + for (i = 0; i < num_smmus; i++) { > + sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); > + > + for (j = 0; j < sdev->idmaps->len; j++) { > + range = &g_array_index(sdev->idmaps, AcpiIortIdMapping, j); > + /* output IORT node is the smmuv3 node */ > + build_iort_id_mapping(table_data, range->input_base, > + range->id_count, sdev->offset); > + } > } > > /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ > @@ -428,8 +465,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > } > > acpi_table_end(linker, &table); > - g_array_free(smmu_idmaps, true); > g_array_free(its_idmaps, true); > + for (i = 0; i < num_smmus; i++) { > + sdev = &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); > + g_array_free(sdev->idmaps, true); > + } > + g_array_free(smmuv3_devs, true); > } > > /* > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 9a6cd085a3..73bd2bd5f2 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1614,6 +1614,7 @@ static void create_pcie(VirtMachineState *vms) > create_smmu(vms, vms->bus); > qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", > 0x0, vms->iommu_phandle, 0x0, 0x10000); > + vms->legacy_smmuv3_present = true; > break; > default: > g_assert_not_reached(); > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > index 9a1b0f53d2..8b1404b5f6 100644 > --- a/include/hw/arm/virt.h > +++ b/include/hw/arm/virt.h > @@ -174,6 +174,7 @@ struct VirtMachineState { > char *oem_id; > char *oem_table_id; > bool ns_el2_virt_timer_irq; > + bool legacy_smmuv3_present; > }; > > #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)