From: Richard Henderson <richard.henderson@linaro.org>
To: Xiong Yining <xiongyining1480@phytium.com.cn>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: rad@semihalf.com, peter.maydell@linaro.org,
quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org
Subject: Re: [PATCH v4 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
Date: Fri, 26 Apr 2024 09:06:21 -0700 [thread overview]
Message-ID: <a25e01c0-5f6e-4568-93ec-970987eb6d07@linaro.org> (raw)
In-Reply-To: <20240426073553.326946-2-xiongyining1480@phytium.com.cn>
On 4/26/24 00:35, Xiong Yining wrote:
> From: xiongyining1480 <xiongyining1480@phytium.com.cn>
>
> Enable CPU cluster support on SbsaQemu platform, so that users can
> specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And
> this topology can be passed to the firmware through DT cpu-map.
>
> Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
> tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
> docs/system/arm/sbsa.rst | 4 ++++
> hw/arm/sbsa-ref.c | 37 ++++++++++++++++++++++++++++++++++++-
> 2 files changed, 40 insertions(+), 1 deletion(-)
Isn't this basically what MPIDR_EL1 is supposed to indicate?
We do not yet implement all of that in QEMU, but should.
Why does the same info need to be replicated in devicetree?
r~
next prev parent reply other threads:[~2024-04-26 16:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 7:35 [PATCH v4 0/1] ARM Sbsa-ref: Enable CPU cluster topology Xiong Yining
2024-04-26 7:35 ` [PATCH v4 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine Xiong Yining
2024-04-26 10:59 ` Marcin Juszkiewicz
2024-04-26 16:06 ` Richard Henderson [this message]
2024-04-28 2:12 ` xiongyining1480
2024-04-29 6:35 ` Marcin Juszkiewicz
2024-04-29 12:21 ` Richard Henderson
2024-05-23 18:47 ` Marcin Juszkiewicz
2024-06-07 8:56 ` xiongyining1480
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