From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary
Date: Tue, 15 Apr 2025 14:04:16 -0700 [thread overview]
Message-ID: <a25e61f7-83a8-4a7d-a436-10f64c7ad2bd@linaro.org> (raw)
In-Reply-To: <20250415192515.232910-44-richard.henderson@linaro.org>
On 4/15/25 12:23, Richard Henderson wrote:
> For TCI, we're losing type information in the interpreter.
> Introduce a tci-specific opcode to handle the difference.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target-has.h | 2 --
> tcg/arm/tcg-target-has.h | 1 -
> tcg/loongarch64/tcg-target-has.h | 2 --
> tcg/mips/tcg-target-has.h | 2 --
> tcg/ppc/tcg-target-has.h | 2 --
> tcg/riscv/tcg-target-has.h | 2 --
> tcg/sparc64/tcg-target-has.h | 2 --
> tcg/tcg-has.h | 15 ++++----
> tcg/tci/tcg-target-has.h | 2 --
> tcg/tcg-op.c | 8 ++---
> tcg/tcg.c | 8 ++---
> tcg/tci.c | 3 +-
> tcg/aarch64/tcg-target.c.inc | 18 ++++++----
> tcg/arm/tcg-target.c.inc | 26 +++++++-------
> tcg/i386/tcg-target.c.inc | 4 +++
> tcg/loongarch64/tcg-target.c.inc | 24 ++++++++-----
> tcg/mips/tcg-target.c.inc | 37 ++++++++++---------
> tcg/ppc/tcg-target.c.inc | 21 ++++++-----
> tcg/riscv/tcg-target.c.inc | 21 ++++++-----
> tcg/s390x/tcg-target.c.inc | 4 +++
> tcg/sparc64/tcg-target.c.inc | 61 +++++++++++++++++---------------
> tcg/tci/tcg-target-opc.h.inc | 1 +
> tcg/tci/tcg-target.c.inc | 17 +++++++--
> 23 files changed, 157 insertions(+), 126 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
> index bde6db8f2a..e961668ef0 100644
> --- a/tcg/aarch64/tcg-target-has.h
> +++ b/tcg/aarch64/tcg-target-has.h
> @@ -13,7 +13,6 @@
> #define have_lse2 (cpuinfo & CPUINFO_LSE2)
>
> /* optional instructions */
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> @@ -30,7 +29,6 @@
> #define TCG_TARGET_HAS_extr_i64_i32 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_bswap16_i64 1
> #define TCG_TARGET_HAS_bswap32_i64 1
> diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
> index ab9b7b6162..6ed2b49c84 100644
> --- a/tcg/arm/tcg-target-has.h
> +++ b/tcg/arm/tcg-target-has.h
> @@ -34,7 +34,6 @@ extern bool use_neon_instructions;
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 1
> #define TCG_TARGET_HAS_muls2_i32 1
> -#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
> #define TCG_TARGET_HAS_rem_i32 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
> index e29c892756..96a99b6d4c 100644
> --- a/tcg/loongarch64/tcg-target-has.h
> +++ b/tcg/loongarch64/tcg-target-has.h
> @@ -11,7 +11,6 @@
>
> /* optional instructions */
> #define TCG_TARGET_HAS_negsetcond_i32 0
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_div2_i32 0
> #define TCG_TARGET_HAS_rot_i32 1
> @@ -29,7 +28,6 @@
>
> /* 64-bit operations */
> #define TCG_TARGET_HAS_negsetcond_i64 0
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_div2_i64 0
> #define TCG_TARGET_HAS_rot_i64 1
> diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
> index ebaaa49cdd..9aa5bf9f1b 100644
> --- a/tcg/mips/tcg-target-has.h
> +++ b/tcg/mips/tcg-target-has.h
> @@ -39,7 +39,6 @@ extern bool use_mips32r2_instructions;
> #endif
>
> /* optional instructions */
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
> #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
> @@ -51,7 +50,6 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_add2_i32 0
> #define TCG_TARGET_HAS_sub2_i32 0
> #define TCG_TARGET_HAS_extr_i64_i32 1
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_add2_i64 0
> #define TCG_TARGET_HAS_sub2_i64 0
> diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
> index bbbd8de2c7..f8e4c0ad3c 100644
> --- a/tcg/ppc/tcg-target-has.h
> +++ b/tcg/ppc/tcg-target-has.h
> @@ -17,7 +17,6 @@
> #define have_vsx (cpuinfo & CPUINFO_VSX)
>
> /* optional instructions */
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 have_isa_3_00
> #define TCG_TARGET_HAS_rot_i32 1
> #define TCG_TARGET_HAS_bswap16_i32 1
> @@ -35,7 +34,6 @@
> #define TCG_TARGET_HAS_add2_i32 0
> #define TCG_TARGET_HAS_sub2_i32 0
> #define TCG_TARGET_HAS_extr_i64_i32 0
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 have_isa_3_00
> #define TCG_TARGET_HAS_rot_i64 1
> #define TCG_TARGET_HAS_bswap16_i64 1
> diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
> index f7e1ef82fc..ae6624b9a4 100644
> --- a/tcg/riscv/tcg-target-has.h
> +++ b/tcg/riscv/tcg-target-has.h
> @@ -11,7 +11,6 @@
>
> /* optional instructions */
> #define TCG_TARGET_HAS_negsetcond_i32 1
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_div2_i32 0
> #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
> @@ -28,7 +27,6 @@
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_negsetcond_i64 1
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_div2_i64 0
> #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
> diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
> index 5a517b6835..35f0dd4230 100644
> --- a/tcg/sparc64/tcg-target-has.h
> +++ b/tcg/sparc64/tcg-target-has.h
> @@ -14,7 +14,6 @@ extern bool use_vis3_instructions;
> #endif
>
> /* optional instructions */
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 0
> #define TCG_TARGET_HAS_rot_i32 0
> #define TCG_TARGET_HAS_bswap16_i32 0
> @@ -31,7 +30,6 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_extr_i64_i32 0
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 0
> #define TCG_TARGET_HAS_rot_i64 0
> #define TCG_TARGET_HAS_bswap16_i64 0
> diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h
> index 3d4c67698f..9680ccfc53 100644
> --- a/tcg/tcg-has.h
> +++ b/tcg/tcg-has.h
> @@ -33,17 +33,16 @@
> #define TCG_TARGET_HAS_sub2_i32 1
> #endif
>
> -/* Only one of DIV or DIV2 should be defined. */
> -#if defined(TCG_TARGET_HAS_div_i32)
> +#ifndef TCG_TARGET_HAS_div2_i32
> #define TCG_TARGET_HAS_div2_i32 0
> -#elif defined(TCG_TARGET_HAS_div2_i32)
> -#define TCG_TARGET_HAS_div_i32 0
> +#endif
> +#ifndef TCG_TARGET_HAS_div2_i64
> +#define TCG_TARGET_HAS_div2_i64 0
> +#endif
> +#ifndef TCG_TARGET_HAS_rem_i32
> #define TCG_TARGET_HAS_rem_i32 0
> #endif
> -#if defined(TCG_TARGET_HAS_div_i64)
> -#define TCG_TARGET_HAS_div2_i64 0
> -#elif defined(TCG_TARGET_HAS_div2_i64)
> -#define TCG_TARGET_HAS_div_i64 0
> +#ifndef TCG_TARGET_HAS_rem_i64
> #define TCG_TARGET_HAS_rem_i64 0
> #endif
>
> diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
> index 0627585097..ccec96b610 100644
> --- a/tcg/tci/tcg-target-has.h
> +++ b/tcg/tci/tcg-target-has.h
> @@ -9,7 +9,6 @@
>
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_clz_i32 1
> @@ -26,7 +25,6 @@
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> -#define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_clz_i64 1
> #define TCG_TARGET_HAS_ctz_i64 1
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 9dba520d40..19be461214 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -635,7 +635,7 @@ void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>
> void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> {
> - if (TCG_TARGET_HAS_div_i32) {
> + if (tcg_op_supported(INDEX_op_divu_i32, TCG_TYPE_I32, 0)) {
> tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
> } else if (TCG_TARGET_HAS_div2_i32) {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> @@ -651,7 +651,7 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> {
> if (TCG_TARGET_HAS_rem_i32) {
> tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
> - } else if (TCG_TARGET_HAS_div_i32) {
> + } else if (tcg_op_supported(INDEX_op_divu_i32, TCG_TYPE_I32, 0)) {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
> tcg_gen_mul_i32(t0, t0, arg2);
> @@ -2003,7 +2003,7 @@ void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>
> void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> {
> - if (TCG_TARGET_HAS_div_i64) {
> + if (tcg_op_supported(INDEX_op_divu_i64, TCG_TYPE_I64, 0)) {
> tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
> } else if (TCG_TARGET_HAS_div2_i64) {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> @@ -2019,7 +2019,7 @@ void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> {
> if (TCG_TARGET_HAS_rem_i64) {
> tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
> - } else if (TCG_TARGET_HAS_div_i64) {
> + } else if (tcg_op_supported(INDEX_op_divu_i64, TCG_TYPE_I64, 0)) {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
> tcg_gen_mul_i64(t0, t0, arg2);
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 0edac806e7..c6eb3c1c2e 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1021,6 +1021,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
> OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
> OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs),
> + OUTOP(INDEX_op_divu_i32, TCGOutOpBinary, outop_divu),
> + OUTOP(INDEX_op_divu_i64, TCGOutOpBinary, outop_divu),
> OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
> OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
> OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
> @@ -2261,8 +2263,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
>
> case INDEX_op_negsetcond_i32:
> return TCG_TARGET_HAS_negsetcond_i32;
> - case INDEX_op_divu_i32:
> - return TCG_TARGET_HAS_div_i32;
> case INDEX_op_rem_i32:
> case INDEX_op_remu_i32:
> return TCG_TARGET_HAS_rem_i32;
> @@ -2323,8 +2323,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
>
> case INDEX_op_negsetcond_i64:
> return TCG_TARGET_HAS_negsetcond_i64;
> - case INDEX_op_divu_i64:
> - return TCG_TARGET_HAS_div_i64;
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i64:
> return TCG_TARGET_HAS_rem_i64;
> @@ -5414,6 +5412,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> case INDEX_op_and:
> case INDEX_op_andc:
> case INDEX_op_divs:
> + case INDEX_op_divu_i32:
> + case INDEX_op_divu_i64:
> case INDEX_op_eqv:
> case INDEX_op_mul:
> case INDEX_op_mulsh:
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 4b3ca53bc5..0691824f97 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -582,7 +582,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> tci_args_rrr(insn, &r0, &r1, &r2);
> regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
> break;
> - case INDEX_op_divu_i32:
> + case INDEX_op_tci_divu32:
> tci_args_rrr(insn, &r0, &r1, &r2);
> regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
> break;
> @@ -1101,6 +1101,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
> case INDEX_op_ctz_i32:
> case INDEX_op_ctz_i64:
> case INDEX_op_tci_divs32:
> + case INDEX_op_tci_divu32:
> tci_args_rrr(insn, &r0, &r1, &r2);
> info->fprintf_func(info->stream, "%-12s %s, %s, %s",
> op_name, str_r(r0), str_r(r1), str_r(r2));
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index 52069f1445..167c51c897 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -2168,6 +2168,17 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tcg_out_insn(s, 3508, UDIV, type, a0, a1, a2);
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_divu,
> +};
> +
> static void tgen_eqv(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2373,11 +2384,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
> tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
> break;
>
> - case INDEX_op_divu_i64:
> - case INDEX_op_divu_i32:
> - tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2);
> - break;
> -
> case INDEX_op_rem_i64:
> case INDEX_op_rem_i32:
> tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP0, a1, a2);
> @@ -3064,8 +3070,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_negsetcond_i64:
> return C_O1_I2(r, r, rC);
>
> - case INDEX_op_divu_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_rem_i32:
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i32:
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index e07e4c06d9..65d0ae83b2 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -937,12 +937,6 @@ static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0,
> (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
> }
>
> -static void tcg_out_udiv(TCGContext *s, ARMCond cond,
> - TCGReg rd, TCGReg rn, TCGReg rm)
> -{
> - tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
> -}
> -
> static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn)
> {
> /* sxtb */
> @@ -1886,6 +1880,19 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + /* udiv */
> + tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8));
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_Dynamic,
> + .base.dynamic_constraint = cset_idiv,
> + .out_rrr = tgen_divu,
> +};
> +
> static const TCGOutOpBinary outop_eqv = {
> .base.static_constraint = C_NotImplemented,
> };
> @@ -2230,10 +2237,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_divu_i32:
> - tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
> - break;
> -
> case INDEX_op_mb:
> tcg_out_mb(s, args[0]);
> break;
> @@ -2277,9 +2280,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ctz_i32:
> return C_O1_I2(r, r, rIK);
>
> - case INDEX_op_divu_i32:
> - return C_O1_I2(r, r, r);
> -
> case INDEX_op_mulu2_i32:
> case INDEX_op_muls2_i32:
> return C_O2_I2(r, r, r, r);
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index e132dd0c88..f258d6383b 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -2637,6 +2637,10 @@ static const TCGOutOpBinary outop_divs = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static const TCGOutOpBinary outop_eqv = {
> .base.static_constraint = C_NotImplemented,
> };
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 3970dcabbc..8adcd030c5 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1331,6 +1331,21 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + if (type == TCG_TYPE_I32) {
> + tcg_out_opc_div_wu(s, a0, a1, a2);
> + } else {
> + tcg_out_opc_div_du(s, a0, a1, a2);
> + }
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_divu,
> +};
> +
> static const TCGOutOpBinary outop_eqv = {
> .base.static_constraint = C_NotImplemented,
> };
> @@ -1674,13 +1689,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_divu_i32:
> - tcg_out_opc_div_wu(s, a0, a1, a2);
> - break;
> - case INDEX_op_divu_i64:
> - tcg_out_opc_div_du(s, a0, a1, a2);
> - break;
> -
> case INDEX_op_rem_i32:
> tcg_out_opc_mod_w(s, a0, a1, a2);
> break;
> @@ -2359,8 +2367,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_setcond_i64:
> return C_O1_I2(r, rz, rJ);
>
> - case INDEX_op_divu_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_rem_i32:
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i32:
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index 7762d88e6b..ab9546f104 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -1733,6 +1733,27 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + if (use_mips32r6_instructions) {
> + if (type == TCG_TYPE_I32) {
> + tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
> + } else {
> + tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
> + }
> + } else {
> + MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU;
> + tcg_out_opc_reg(s, insn, 0, a1, a2);
> + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
> + }
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_divu,
> +};
> +
> static const TCGOutOpBinary outop_eqv = {
> .base.static_constraint = C_NotImplemented,
> };
> @@ -1960,13 +1981,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, i1, a0, a1, a2);
> break;
>
> - case INDEX_op_divu_i32:
> - if (use_mips32r6_instructions) {
> - tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
> - break;
> - }
> - i1 = OPC_DIVU, i2 = OPC_MFLO;
> - goto do_hilo1;
> case INDEX_op_rem_i32:
> if (use_mips32r6_instructions) {
> tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
> @@ -1981,13 +1995,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> i1 = OPC_DIVU, i2 = OPC_MFHI;
> goto do_hilo1;
> - case INDEX_op_divu_i64:
> - if (use_mips32r6_instructions) {
> - tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
> - break;
> - }
> - i1 = OPC_DDIVU, i2 = OPC_MFLO;
> - goto do_hilo1;
> case INDEX_op_rem_i64:
> if (use_mips32r6_instructions) {
> tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
> @@ -2260,11 +2267,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(rz, r);
>
> - case INDEX_op_divu_i32:
> case INDEX_op_rem_i32:
> case INDEX_op_remu_i32:
> case INDEX_op_setcond_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i64:
> case INDEX_op_setcond_i64:
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 9fdf8df082..b347595131 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -2972,6 +2972,18 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + uint32_t insn = type == TCG_TYPE_I32 ? DIVWU : DIVDU;
> + tcg_out32(s, insn | TAB(a0, a1, a2));
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_divu,
> +};
> +
> static const TCGOutOpBinary outop_eqv = {
> .base.static_constraint = C_O1_I2(r, r, r),
> .out_rrr = tgen_eqv,
> @@ -3221,10 +3233,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
> break;
>
> - case INDEX_op_divu_i32:
> - tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
> - break;
> -
> case INDEX_op_rem_i32:
> tcg_out32(s, MODSW | TAB(args[0], args[1], args[2]));
> break;
> @@ -3325,9 +3333,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_divu_i64:
> - tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
> - break;
> case INDEX_op_rem_i64:
> tcg_out32(s, MODSD | TAB(args[0], args[1], args[2]));
> break;
> @@ -4189,10 +4194,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_rotr_i64:
> return C_O1_I2(r, r, ri);
>
> - case INDEX_op_divu_i32:
> case INDEX_op_rem_i32:
> case INDEX_op_remu_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i64:
> return C_O1_I2(r, r, r);
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 15925729dc..74fa38d273 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -2009,6 +2009,18 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_DIVUW : OPC_DIVU;
> + tcg_out_opc_reg(s, insn, a0, a1, a2);
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_divu,
> +};
> +
> static void tgen_eqv(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2213,13 +2225,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_ldst(s, OPC_SD, a0, a1, a2);
> break;
>
> - case INDEX_op_divu_i32:
> - tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
> - break;
> - case INDEX_op_divu_i64:
> - tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
> - break;
> -
> case INDEX_op_rem_i32:
> tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
> break;
> @@ -2735,10 +2740,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_negsetcond_i64:
> return C_O1_I2(r, r, rI);
>
> - case INDEX_op_divu_i32:
> case INDEX_op_rem_i32:
> case INDEX_op_remu_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i64:
> return C_O1_I2(r, rz, rz);
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index fd0e717c49..f55309f48e 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -2246,6 +2246,10 @@ static const TCGOutOpBinary outop_divs = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static void tgen_eqv(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index 779d0ce882..3a3372d7aa 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -596,21 +596,6 @@ static void tcg_out_sety(TCGContext *s, TCGReg rs)
> tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
> }
>
> -static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
> - int32_t val2, int val2const, int uns)
> -{
> - /* Load Y with the sign/zero extension of RS1 to 64-bits. */
> - if (uns) {
> - tcg_out_sety(s, TCG_REG_G0);
> - } else {
> - tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
> - tcg_out_sety(s, TCG_REG_T1);
> - }
> -
> - tcg_out_arithc(s, rd, rs1, val2, val2const,
> - uns ? ARITH_UDIV : ARITH_SDIV);
> -}
> -
> static const uint8_t tcg_cond_to_bcond[16] = {
> [TCG_COND_EQ] = COND_E,
> [TCG_COND_NE] = COND_NE,
> @@ -1367,6 +1352,39 @@ static const TCGOutOpBinary outop_divs = {
> .out_rri = tgen_divsi,
> };
>
> +static void tgen_divu_rJ(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGArg a2, bool c2)
> +{
> + uint32_t insn;
> +
> + if (type == TCG_TYPE_I32) {
> + /* Load Y with the zero extension to 64-bits. */
> + tcg_out_sety(s, TCG_REG_G0);
> + insn = ARITH_UDIV;
> + } else {
> + insn = ARITH_UDIVX;
> + }
> + tcg_out_arithc(s, a0, a1, a2, c2, insn);
> +}
> +
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + tgen_divu_rJ(s, type, a0, a1, a2, false);
> +}
> +
> +static void tgen_divui(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, tcg_target_long a2)
> +{
> + tgen_divu_rJ(s, type, a0, a1, a2, true);
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, rJ),
> + .out_rrr = tgen_divu,
> + .out_rri = tgen_divui,
> +};
> +
> static const TCGOutOpBinary outop_eqv = {
> .base.static_constraint = C_NotImplemented,
> };
> @@ -1566,10 +1584,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> c = SHIFT_SRA;
> goto do_shift32;
>
> - case INDEX_op_divu_i32:
> - tcg_out_div32(s, a0, a1, a2, c2, 1);
> - break;
> -
> case INDEX_op_brcond_i32:
> tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
> break;
> @@ -1638,9 +1652,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> case INDEX_op_sar_i64:
> c = SHIFT_SRAX;
> goto do_shift64;
> - case INDEX_op_divu_i64:
> - c = ARITH_UDIVX;
> - goto gen_arith;
>
> case INDEX_op_brcond_i64:
> tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
> @@ -1663,10 +1674,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const_args[4], args[5], const_args[5], true);
> break;
>
> - gen_arith:
> - tcg_out_arithc(s, a0, a1, a2, c2, c);
> - break;
> -
> case INDEX_op_mb:
> tcg_out_mb(s, a0);
> break;
> @@ -1728,8 +1735,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_qemu_st_i64:
> return C_O0_I2(rz, r);
>
> - case INDEX_op_divu_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_shl_i32:
> case INDEX_op_shl_i64:
> case INDEX_op_shr_i32:
> diff --git a/tcg/tci/tcg-target-opc.h.inc b/tcg/tci/tcg-target-opc.h.inc
> index f503374643..43c07a269f 100644
> --- a/tcg/tci/tcg-target-opc.h.inc
> +++ b/tcg/tci/tcg-target-opc.h.inc
> @@ -3,3 +3,4 @@
> DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT)
> DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT)
> DEF(tci_divs32, 1, 2, 0, TCG_OPF_NOT_PRESENT)
> +DEF(tci_divu32, 1, 2, 0, TCG_OPF_NOT_PRESENT)
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 4a556e2ce7..18a10156a6 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -79,8 +79,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_st_i64:
> return C_O0_I2(r, r);
>
> - case INDEX_op_divu_i32:
> - case INDEX_op_divu_i64:
> case INDEX_op_rem_i32:
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i32:
> @@ -660,6 +658,20 @@ static const TCGOutOpBinary outop_divs = {
> .out_rrr = tgen_divs,
> };
>
> +static void tgen_divu(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> + TCGOpcode opc = (type == TCG_TYPE_I32
> + ? INDEX_op_tci_divu32
> + : INDEX_op_divu_i64);
> + tcg_out_op_rrr(s, opc, a0, a1, a2);
> +}
> +
> +static const TCGOutOpBinary outop_divu = {
> + .base.static_constraint = C_O1_I2(r, r, r),
> + .out_rrr = tgen_divu,
> +};
> +
> static void tgen_eqv(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -823,7 +835,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> CASE_32_64(sar)
> CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */
> CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */
> - CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
> CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
> CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
> CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-04-15 21:04 UTC|newest]
Thread overview: 316+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 19:22 [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Richard Henderson
2025-04-15 19:22 ` [PATCH v4 001/163] tcg: Add all_outop[] Richard Henderson
2025-04-15 19:22 ` [PATCH v4 002/163] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-15 19:22 ` [PATCH v4 003/163] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-15 19:22 ` [PATCH v4 004/163] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 005/163] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 006/163] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 007/163] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 008/163] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 009/163] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-15 19:22 ` [PATCH v4 010/163] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-15 19:22 ` [PATCH v4 011/163] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 012/163] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 013/163] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 014/163] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 015/163] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-15 19:22 ` [PATCH v4 016/163] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 017/163] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 018/163] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 019/163] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 020/163] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 021/163] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 022/163] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 023/163] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 024/163] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 025/163] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 026/163] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 027/163] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 028/163] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-15 19:23 ` [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-15 21:00 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 030/163] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 031/163] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 032/163] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 033/163] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 034/163] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 035/163] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 036/163] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 037/163] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 038/163] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 039/163] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 040/163] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 041/163] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-15 21:02 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-22 15:27 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier [this message]
2025-04-15 19:23 ` [PATCH v4 044/163] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 045/163] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-15 19:23 ` [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 048/163] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-15 21:07 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 052/163] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 053/163] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 054/163] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-15 21:08 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 056/163] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-15 21:09 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 058/163] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-15 21:11 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-15 21:12 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 063/163] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-15 21:13 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 065/163] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-15 21:14 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-15 21:15 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:18 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 071/163] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 072/163] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-15 21:19 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 073/163] tcg/mips: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 074/163] tcg/tci: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-22 15:28 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 075/163] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-22 15:35 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-15 21:21 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-15 21:22 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-15 21:23 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-15 21:24 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-15 21:25 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 081/163] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-15 21:26 ` Pierrick Bouvier
2025-04-16 14:39 ` Nicholas Piggin
2025-04-16 18:57 ` Richard Henderson
2025-04-15 19:23 ` [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 084/163] tcg/ppc: " Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-16 14:43 ` Nicholas Piggin
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-15 21:37 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-15 21:39 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-15 21:40 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-15 21:41 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-15 21:46 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-15 21:47 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-15 21:50 ` Pierrick Bouvier
2025-06-09 13:52 ` Andrea Bolognani
2025-06-26 16:20 ` Andrea Bolognani
2025-06-27 13:16 ` Richard Henderson
2025-06-27 14:29 ` Philippe Mathieu-Daudé
2025-06-30 12:08 ` Andrea Bolognani
2025-04-15 19:24 ` [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-15 21:51 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 098/163] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-15 21:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 099/163] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-15 21:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 100/163] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-15 21:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-15 21:59 ` Pierrick Bouvier
2025-08-28 7:37 ` Michael Tokarev
2025-04-15 19:24 ` [PATCH v4 102/163] tcg/aarch64: Improve deposit Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 103/163] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-15 19:24 ` [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-15 22:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 107/163] tcg: Expand fallback sub2 " Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 110/163] tcg/riscv: " Richard Henderson
2025-04-15 22:05 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-15 22:07 ` Pierrick Bouvier
2025-04-16 6:37 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-15 22:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 113/163] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-16 19:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 114/163] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-16 18:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 115/163] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-16 19:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 116/163] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-16 19:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 117/163] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 118/163] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 119/163] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 122/163] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-22 16:30 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 124/163] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-16 19:00 ` Pierrick Bouvier
2025-04-22 16:15 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 125/163] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:17 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 126/163] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:28 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 127/163] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:32 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 128/163] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-16 14:08 ` Nicholas Piggin
2025-04-16 19:08 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 129/163] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 130/163] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:34 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 131/163] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 132/163] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:38 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 133/163] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:10 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:13 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 135/163] tcg/arm: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 136/163] tcg/arm: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 137/163] tcg/ppc: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 138/163] tcg/ppc: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 139/163] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 140/163] tcg/s390: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 141/163] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 142/163] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-16 6:40 ` Philippe Mathieu-Daudé
2025-04-16 19:19 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 145/163] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 146/163] tcg/sparc64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 147/163] tcg/tci: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:36 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 149/163] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-22 16:42 ` Philippe Mathieu-Daudé
2025-04-22 17:10 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 150/163] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-22 16:44 ` Philippe Mathieu-Daudé
2025-04-15 19:25 ` [PATCH v4 151/163] tcg: Formalize tcg_out_br Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-16 20:45 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 153/163] tcg: Assign TCGOP_TYPE in liveness_pass_2 Richard Henderson
2025-04-16 20:46 ` Pierrick Bouvier
2025-04-18 10:46 ` Nicholas Piggin
2025-04-21 16:28 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 154/163] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-16 20:52 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 155/163] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 156/163] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 157/163] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-16 7:05 ` Philippe Mathieu-Daudé
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 20:54 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 19:24 ` Richard Henderson
2025-04-16 20:55 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 160/163] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-16 20:56 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 161/163] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-16 20:57 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 162/163] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-16 20:58 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 163/163] tcg: Remove tcg_out_op Richard Henderson
2025-04-16 19:04 ` Pierrick Bouvier
2025-04-16 13:24 ` [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Nicholas Piggin
2025-04-16 23:38 ` Pierrick Bouvier
2025-04-17 0:18 ` Richard Henderson
2025-04-17 0:49 ` Pierrick Bouvier
2025-04-17 12:02 ` BALATON Zoltan
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