Re: [PATCH v3 23/51] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

[Richard Henderson <richard.henderson@linaro.org>]

On 6/21/22 10:23, Peter Maydell wrote:
>> +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a)
>> +{
>> +    if (!dc_isar_feature(aa64_sme, s)) {
>> +        return false;
>> +    }
>> +    if (sme_enabled_check(s)) {
>> +        TCGv_i64 reg = cpu_reg(s, a->rd);
>> +        tcg_gen_movi_i64(reg, a->imm * s->svl);
>> +    }
>> +    return true;
>> +}
> 
> I think we should define functions that parallel the SVE
> vec_full_reg_size() and pred_full_reg_size() rather than directly
> looking at s->svl, for consistency with how we did the SVE code.

I had actually been thinking of removing vec_full_reg_size, at least within SVE. 
However... done.  I've propagated the new predicates forward through the following patches 
as well.


r~