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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id v4-20020a05600c470400b0040e45799541sm6240022wmo.15.2024.01.11.07.49.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 07:49:20 -0800 (PST) Message-ID: Subject: Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type From: Rob Bradford To: Daniel Henrique Barboza , Andrew Jones Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com Date: Thu, 11 Jan 2024 15:49:19 +0000 In-Reply-To: References: <20240109171848.32237-1-rbradford@rivosinc.com> <20240109171848.32237-4-rbradford@rivosinc.com> <20240111-558c99b8f3be4297e9ae4118@orel> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 (3.48.4-1.module_f38+17164+63eeee4a) MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 2024-01-11 at 11:53 -0300, Daniel Henrique Barboza wrote: >=20 >=20 > On 1/11/24 10:02, Andrew Jones wrote: > > On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza > > wrote: > > >=20 > > >=20 > > > On 1/9/24 14:07, Rob Bradford wrote: > > > > Signed-off-by: Rob Bradford > > > > --- > > > > =C2=A0=C2=A0 target/riscv/tcg/tcg-cpu.c | 3 ++- > > > > =C2=A0=C2=A0 1 file changed, 2 insertions(+), 1 deletion(-) > > > >=20 > > > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg- > > > > cpu.c > > > > index f10871d352..9705daec93 100644 > > > > --- a/target/riscv/tcg/tcg-cpu.c > > > > +++ b/target/riscv/tcg/tcg-cpu.c > > > > @@ -999,7 +999,8 @@ static void > > > > riscv_init_max_cpu_extensions(Object *obj) > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const RISCVCPUMultiExtConfig *= prop; > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Enable RVG, RVJ and RVV tha= t are disabled by default > > > > */ > > > > -=C2=A0=C2=A0=C2=A0 riscv_cpu_set_misa(env, env->misa_mxl, env->mis= a_ext | RVG > > > > | RVJ | RVV); > > > > +=C2=A0=C2=A0=C2=A0 riscv_cpu_set_misa(env, env->misa_mxl, > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 env->mis= a_ext | RVG | RVJ | RVV | RVB); > > >=20 > > > I'm aware that we decided a while ago the 'max' CPU could only > > > have non-vendor and > > > non-experimental extensions enabled. RVB is experimental, so in > > > theory we shouldn't > > > enable it. > > >=20 > > > But RVB is an alias for zba, zbb and zbs, extensions that the > > > 'max' CPU is already > > > enabling. In this case I think it's sensible to enable RVB here > > > since it would > > > just=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 > > > reflect stuff that it's already happening. > >=20 > > It's also setting the B bit in misa, which, until this spec is at > > least > > frozen, is a reserved bit and reserved bits "must return zero when > > read". >=20 > This is a side effect that I wasn't aware of. >=20 > Rob, given that the 'max' CPU already has the zb* extensions enabled, > is there any > other gain in enabling RVB in this CPU? If there isn't I'd rather > leave this one > out for now. >=20 It seems completely reasonable to me to drop it for now. Thanks for all the feedback, Rob >=20 > Thanks, >=20 > Daniel >=20 >=20 > >=20 > > I don't want to stand in the way of progress and it seems 99.9% > > likely > > that the spec will be frozen and ratified, but, if we want to stick > > to > > our policies (which we should document), then even the 'max' cpu > > type > > should require x-b be added to the command line if it wants the B > > bit > > set in misa. > >=20 > > Thanks, > > drew