From: Salil Mehta via <qemu-devel@nongnu.org> To: Gavin Shan <gshan@redhat.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-arm@nongnu.org" <qemu-arm@nongnu.org> Cc: "maz@kernel.org" <maz@kernel.org>, "jean-philippe@linaro.org" <jean-philippe@linaro.org>, Jonathan Cameron <jonathan.cameron@huawei.com>, "lpieralisi@kernel.org" <lpieralisi@kernel.org>, "peter.maydell@linaro.org" <peter.maydell@linaro.org>, "richard.henderson@linaro.org" <richard.henderson@linaro.org>, "imammedo@redhat.com" <imammedo@redhat.com>, "andrew.jones@linux.dev" <andrew.jones@linux.dev>, "david@redhat.com" <david@redhat.com>, "philmd@linaro.org" <philmd@linaro.org>, "eric.auger@redhat.com" <eric.auger@redhat.com>, "oliver.upton@linux.dev" <oliver.upton@linux.dev>, "pbonzini@redhat.com" <pbonzini@redhat.com>, "mst@redhat.com" <mst@redhat.com>, "will@kernel.org" <will@kernel.org>, "rafael@kernel.org" <rafael@kernel.org>, "alex.bennee@linaro.org" <alex.bennee@linaro.org>, "linux@armlinux.org.uk" <linux@armlinux.org.uk>, "darren@os.amperecomputing.com" <darren@os.amperecomputing.com>, "ilkka@os.amperecomputing.com" <ilkka@os.amperecomputing.com>, "vishnu@os.amperecomputing.com" <vishnu@os.amperecomputing.com>, "karl.heubaum@oracle.com" <karl.heubaum@oracle.com>, "miguel.luis@oracle.com" <miguel.luis@oracle.com>, "salil.mehta@opnsrc.net" <salil.mehta@opnsrc.net>, zhukeqian <zhukeqian1@huawei.com>, "wangxiongfeng (C)" <wangxiongfeng2@huawei.com>, "wangyanan (Y)" <wangyanan55@huawei.com>, "jiakernel2@gmail.com" <jiakernel2@gmail.com>, "maobibo@loongson.cn" <maobibo@loongson.cn>, "lixianglai@loongson.cn" <lixianglai@loongson.cn>, Linuxarm <linuxarm@huawei.com> Subject: RE: [PATCH V2 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Tue, 3 Oct 2023 11:33:20 +0000 [thread overview] Message-ID: <a2f6c1632bd74c4581a80f1cb765292c@huawei.com> (raw) In-Reply-To: <5dc18701-973b-bd1c-8704-479ea67a7be8@redhat.com> > From: Gavin Shan <gshan@redhat.com> > Sent: Tuesday, October 3, 2023 1:09 AM > To: Salil Mehta <salil.mehta@huawei.com>; qemu-devel@nongnu.org; qemu- > arm@nongnu.org > Cc: maz@kernel.org; jean-philippe@linaro.org; Jonathan Cameron > <jonathan.cameron@huawei.com>; lpieralisi@kernel.org; > peter.maydell@linaro.org; richard.henderson@linaro.org; > imammedo@redhat.com; andrew.jones@linux.dev; david@redhat.com; > philmd@linaro.org; eric.auger@redhat.com; oliver.upton@linux.dev; > pbonzini@redhat.com; mst@redhat.com; will@kernel.org; rafael@kernel.org; > alex.bennee@linaro.org; linux@armlinux.org.uk; > darren@os.amperecomputing.com; ilkka@os.amperecomputing.com; > vishnu@os.amperecomputing.com; karl.heubaum@oracle.com; > miguel.luis@oracle.com; salil.mehta@opnsrc.net; zhukeqian > <zhukeqian1@huawei.com>; wangxiongfeng (C) <wangxiongfeng2@huawei.com>; > wangyanan (Y) <wangyanan55@huawei.com>; jiakernel2@gmail.com; > maobibo@loongson.cn; lixianglai@loongson.cn; Linuxarm <linuxarm@huawei.com> > Subject: Re: [PATCH V2 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev > change > > On 9/30/23 10:19, Salil Mehta wrote: > > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on > > PCI and is IO port based and hence existing cpus AML code assumes _CRS objects > > would evaluate to a system resource which describes IO Port address. But on ARM > > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence > > _CRS object should evaluate to system resource which describes memory-mapped > > base address. > > > > This cpus AML code change updates the existing inerface of the build cpus AML > > function to accept both IO/MEMORY type regions and update the _CRS object > > correspondingly. > > > > Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com> > > Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> > > Signed-off-by: Salil Mehta <salil.mehta@huawei.com> > > --- > > hw/acpi/cpu.c | 23 ++++++++++++++++------- > > hw/i386/acpi-build.c | 2 +- > > include/hw/acpi/cpu.h | 5 +++-- > > 3 files changed, 20 insertions(+), 10 deletions(-) > > > > With commit log improved to address Jonathan's comments why > @event_handler_method > won't be needed on aarch64: > > Reviewed-by: Gavin Shan <gshan@redhat.com> Thanks Salil. > > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c > > index 45defdc0e2..66a71660ec 100644 > > --- a/hw/acpi/cpu.c > > +++ b/hw/acpi/cpu.c > > @@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug = { > > #define CPU_FW_EJECT_EVENT "CEJF" > > > > void build_cpus_aml(Aml *table, MachineState *machine, > CPUHotplugFeatures opts, > > - hwaddr io_base, > > + hwaddr base_addr, > > const char *res_root, > > - const char *event_handler_method) > > + const char *event_handler_method, > > + AmlRegionSpace rs) > > { > > Aml *ifctx; > > Aml *field; > > @@ -367,13 +368,19 @@ void build_cpus_aml(Aml *table, MachineState > *machine, CPUHotplugFeatures opts, > > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); > > > > crs = aml_resource_template(); > > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, > > + if (rs == AML_SYSTEM_IO) { > > + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, > 1, > > ACPI_CPU_HOTPLUG_REG_LEN)); > > + } else { > > + aml_append(crs, aml_memory32_fixed(base_addr, > > + ACPI_CPU_HOTPLUG_REG_LEN, > AML_READ_WRITE)); > > + } > > + > > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); > > > > /* declare CPU hotplug MMIO region with related access fields > */ > > aml_append(cpu_ctrl_dev, > > - aml_operation_region("PRST", AML_SYSTEM_IO, > aml_int(io_base), > > + aml_operation_region("PRST", rs, aml_int(base_addr), > > ACPI_CPU_HOTPLUG_REG_LEN)); > > > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, > > @@ -699,9 +706,11 @@ void build_cpus_aml(Aml *table, MachineState > *machine, CPUHotplugFeatures opts, > > aml_append(sb_scope, cpus_dev); > > aml_append(table, sb_scope); > > > > - method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); > > - aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); > > - aml_append(table, method); > > + if (event_handler_method) { > > + method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); > > + aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); > > + aml_append(table, method); > > + } > > > > g_free(cphp_res_path); > > } > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index 4d2d40bab5..611d3d044d 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -1550,7 +1550,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > .fw_unplugs_cpu = pm->smi_on_cpu_unplug, > > }; > > build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, > > - "\\_SB.PCI0", "\\_GPE._E02"); > > + "\\_SB.PCI0", "\\_GPE._E02", AML_SYSTEM_IO); > > } > > > > if (pcms->memhp_io_base && nr_mem) { > > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h > > index 999caaf510..b87ebfdf4b 100644 > > --- a/include/hw/acpi/cpu.h > > +++ b/include/hw/acpi/cpu.h > > @@ -56,9 +56,10 @@ typedef struct CPUHotplugFeatures { > > } CPUHotplugFeatures; > > > > void build_cpus_aml(Aml *table, MachineState *machine, > CPUHotplugFeatures opts, > > - hwaddr io_base, > > + hwaddr base_addr, > > const char *res_root, > > - const char *event_handler_method); > > + const char *event_handler_method, > > + AmlRegionSpace rs); > > > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList > ***list); > > > > Thanks, > Gavin
WARNING: multiple messages have this Message-ID (diff)
From: Salil Mehta <salil.mehta@huawei.com> To: Gavin Shan <gshan@redhat.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-arm@nongnu.org" <qemu-arm@nongnu.org> Cc: "maz@kernel.org" <maz@kernel.org>, "jean-philippe@linaro.org" <jean-philippe@linaro.org>, Jonathan Cameron <jonathan.cameron@huawei.com>, "lpieralisi@kernel.org" <lpieralisi@kernel.org>, "peter.maydell@linaro.org" <peter.maydell@linaro.org>, "richard.henderson@linaro.org" <richard.henderson@linaro.org>, "imammedo@redhat.com" <imammedo@redhat.com>, "andrew.jones@linux.dev" <andrew.jones@linux.dev>, "david@redhat.com" <david@redhat.com>, "philmd@linaro.org" <philmd@linaro.org>, "eric.auger@redhat.com" <eric.auger@redhat.com>, "oliver.upton@linux.dev" <oliver.upton@linux.dev>, "pbonzini@redhat.com" <pbonzini@redhat.com>, "mst@redhat.com" <mst@redhat.com>, "will@kernel.org" <will@kernel.org>, "rafael@kernel.org" <rafael@kernel.org>, "alex.bennee@linaro.org" <alex.bennee@linaro.org>, "linux@armlinux.org.uk" <linux@armlinux.org.uk>, "darren@os.amperecomputing.com" <darren@os.amperecomputing.com>, "ilkka@os.amperecomputing.com" <ilkka@os.amperecomputing.com>, "vishnu@os.amperecomputing.com" <vishnu@os.amperecomputing.com>, "karl.heubaum@oracle.com" <karl.heubaum@oracle.com>, "miguel.luis@oracle.com" <miguel.luis@oracle.com>, "salil.mehta@opnsrc.net" <salil.mehta@opnsrc.net>, zhukeqian <zhukeqian1@huawei.com>, "wangxiongfeng (C)" <wangxiongfeng2@huawei.com>, "wangyanan (Y)" <wangyanan55@huawei.com>, "jiakernel2@gmail.com" <jiakernel2@gmail.com>, "maobibo@loongson.cn" <maobibo@loongson.cn>, "lixianglai@loongson.cn" <lixianglai@loongson.cn>, Linuxarm <linuxarm@huawei.com> Subject: RE: [PATCH V2 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Tue, 3 Oct 2023 11:33:20 +0000 [thread overview] Message-ID: <a2f6c1632bd74c4581a80f1cb765292c@huawei.com> (raw) Message-ID: <20231003113320.faRqQ3zJ4ZmheCbyrQjR5vDOIW9mjhk3Y9uyJndrZ7M@z> (raw) In-Reply-To: <5dc18701-973b-bd1c-8704-479ea67a7be8@redhat.com> > From: Gavin Shan <gshan@redhat.com> > Sent: Tuesday, October 3, 2023 1:09 AM > To: Salil Mehta <salil.mehta@huawei.com>; qemu-devel@nongnu.org; qemu- > arm@nongnu.org > Cc: maz@kernel.org; jean-philippe@linaro.org; Jonathan Cameron > <jonathan.cameron@huawei.com>; lpieralisi@kernel.org; > peter.maydell@linaro.org; richard.henderson@linaro.org; > imammedo@redhat.com; andrew.jones@linux.dev; david@redhat.com; > philmd@linaro.org; eric.auger@redhat.com; oliver.upton@linux.dev; > pbonzini@redhat.com; mst@redhat.com; will@kernel.org; rafael@kernel.org; > alex.bennee@linaro.org; linux@armlinux.org.uk; > darren@os.amperecomputing.com; ilkka@os.amperecomputing.com; > vishnu@os.amperecomputing.com; karl.heubaum@oracle.com; > miguel.luis@oracle.com; salil.mehta@opnsrc.net; zhukeqian > <zhukeqian1@huawei.com>; wangxiongfeng (C) <wangxiongfeng2@huawei.com>; > wangyanan (Y) <wangyanan55@huawei.com>; jiakernel2@gmail.com; > maobibo@loongson.cn; lixianglai@loongson.cn; Linuxarm <linuxarm@huawei.com> > Subject: Re: [PATCH V2 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev > change > > On 9/30/23 10:19, Salil Mehta wrote: > > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on > > PCI and is IO port based and hence existing cpus AML code assumes _CRS objects > > would evaluate to a system resource which describes IO Port address. But on ARM > > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence > > _CRS object should evaluate to system resource which describes memory-mapped > > base address. > > > > This cpus AML code change updates the existing inerface of the build cpus AML > > function to accept both IO/MEMORY type regions and update the _CRS object > > correspondingly. > > > > Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com> > > Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> > > Signed-off-by: Salil Mehta <salil.mehta@huawei.com> > > --- > > hw/acpi/cpu.c | 23 ++++++++++++++++------- > > hw/i386/acpi-build.c | 2 +- > > include/hw/acpi/cpu.h | 5 +++-- > > 3 files changed, 20 insertions(+), 10 deletions(-) > > > > With commit log improved to address Jonathan's comments why > @event_handler_method > won't be needed on aarch64: > > Reviewed-by: Gavin Shan <gshan@redhat.com> Thanks Salil. > > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c > > index 45defdc0e2..66a71660ec 100644 > > --- a/hw/acpi/cpu.c > > +++ b/hw/acpi/cpu.c > > @@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug = { > > #define CPU_FW_EJECT_EVENT "CEJF" > > > > void build_cpus_aml(Aml *table, MachineState *machine, > CPUHotplugFeatures opts, > > - hwaddr io_base, > > + hwaddr base_addr, > > const char *res_root, > > - const char *event_handler_method) > > + const char *event_handler_method, > > + AmlRegionSpace rs) > > { > > Aml *ifctx; > > Aml *field; > > @@ -367,13 +368,19 @@ void build_cpus_aml(Aml *table, MachineState > *machine, CPUHotplugFeatures opts, > > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); > > > > crs = aml_resource_template(); > > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, > > + if (rs == AML_SYSTEM_IO) { > > + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, > 1, > > ACPI_CPU_HOTPLUG_REG_LEN)); > > + } else { > > + aml_append(crs, aml_memory32_fixed(base_addr, > > + ACPI_CPU_HOTPLUG_REG_LEN, > AML_READ_WRITE)); > > + } > > + > > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); > > > > /* declare CPU hotplug MMIO region with related access fields > */ > > aml_append(cpu_ctrl_dev, > > - aml_operation_region("PRST", AML_SYSTEM_IO, > aml_int(io_base), > > + aml_operation_region("PRST", rs, aml_int(base_addr), > > ACPI_CPU_HOTPLUG_REG_LEN)); > > > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, > > @@ -699,9 +706,11 @@ void build_cpus_aml(Aml *table, MachineState > *machine, CPUHotplugFeatures opts, > > aml_append(sb_scope, cpus_dev); > > aml_append(table, sb_scope); > > > > - method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); > > - aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); > > - aml_append(table, method); > > + if (event_handler_method) { > > + method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); > > + aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); > > + aml_append(table, method); > > + } > > > > g_free(cphp_res_path); > > } > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index 4d2d40bab5..611d3d044d 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -1550,7 +1550,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > .fw_unplugs_cpu = pm->smi_on_cpu_unplug, > > }; > > build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, > > - "\\_SB.PCI0", "\\_GPE._E02"); > > + "\\_SB.PCI0", "\\_GPE._E02", AML_SYSTEM_IO); > > } > > > > if (pcms->memhp_io_base && nr_mem) { > > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h > > index 999caaf510..b87ebfdf4b 100644 > > --- a/include/hw/acpi/cpu.h > > +++ b/include/hw/acpi/cpu.h > > @@ -56,9 +56,10 @@ typedef struct CPUHotplugFeatures { > > } CPUHotplugFeatures; > > > > void build_cpus_aml(Aml *table, MachineState *machine, > CPUHotplugFeatures opts, > > - hwaddr io_base, > > + hwaddr base_addr, > > const char *res_root, > > - const char *event_handler_method); > > + const char *event_handler_method, > > + AmlRegionSpace rs); > > > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList > ***list); > > > > Thanks, > Gavin
next prev parent reply other threads:[~2023-10-03 11:33 UTC|newest] Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-30 0:19 [PATCH V2 00/10] Add architecture agnostic code to support vCPU Hotplug Salil Mehta via 2023-09-30 0:19 ` [PATCH V2 01/10] accel/kvm: Extract common KVM vCPU {creation, parking} code Salil Mehta via 2023-10-02 15:53 ` [PATCH V2 01/10] accel/kvm: Extract common KVM vCPU {creation,parking} code Jonathan Cameron via 2023-10-02 15:53 ` Jonathan Cameron 2023-10-03 11:05 ` Salil Mehta via 2023-10-03 11:05 ` Salil Mehta 2023-10-03 11:51 ` Jonathan Cameron via 2023-10-03 11:51 ` Jonathan Cameron 2023-10-03 12:27 ` Salil Mehta via 2023-10-03 12:27 ` Salil Mehta 2023-10-02 23:17 ` Gavin Shan 2023-10-03 11:22 ` Salil Mehta via 2023-10-03 11:22 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 02/10] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file Salil Mehta via 2023-10-02 15:54 ` Jonathan Cameron via 2023-10-02 15:54 ` Jonathan Cameron 2023-10-03 11:24 ` Salil Mehta via 2023-10-03 11:24 ` Salil Mehta 2023-10-02 23:19 ` Gavin Shan 2023-10-03 11:24 ` Salil Mehta via 2023-10-03 11:24 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 03/10] hw/acpi: Add ACPI CPU hotplug init stub Salil Mehta via 2023-10-02 16:00 ` Jonathan Cameron via 2023-10-02 16:00 ` Jonathan Cameron 2023-10-03 11:27 ` Salil Mehta via 2023-10-03 11:27 ` Salil Mehta 2023-10-02 23:25 ` Gavin Shan 2023-10-03 11:28 ` Salil Mehta via 2023-10-03 11:28 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 04/10] hw/acpi: Init GED framework with cpu hotplug events Salil Mehta via 2023-10-02 16:07 ` Jonathan Cameron via 2023-10-02 16:07 ` Jonathan Cameron 2023-10-03 11:29 ` Salil Mehta via 2023-10-03 11:29 ` Salil Mehta 2023-10-02 23:28 ` Gavin Shan 2023-10-03 11:30 ` Salil Mehta via 2023-10-03 11:30 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Salil Mehta via 2023-10-02 16:09 ` Jonathan Cameron via 2023-10-02 16:09 ` Jonathan Cameron 2023-10-03 11:31 ` Salil Mehta via 2023-10-03 11:31 ` Salil Mehta 2023-10-03 0:09 ` Gavin Shan 2023-10-03 11:33 ` Salil Mehta via [this message] 2023-10-03 11:33 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 06/10] hw/acpi: Update GED _EVT method AML with cpu scan Salil Mehta via 2023-10-02 16:14 ` Jonathan Cameron via 2023-10-02 16:14 ` Jonathan Cameron 2023-10-03 11:43 ` Salil Mehta via 2023-10-03 11:43 ` Salil Mehta 2023-10-03 11:53 ` Jonathan Cameron via 2023-10-03 11:53 ` Jonathan Cameron 2023-10-03 12:13 ` Salil Mehta via 2023-10-03 12:13 ` Salil Mehta 2023-10-03 0:10 ` Gavin Shan 2023-10-03 11:43 ` Salil Mehta via 2023-10-03 11:43 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 07/10] hw/acpi: Update ACPI GED framework to support vCPU Hotplug Salil Mehta via 2023-10-02 16:16 ` Jonathan Cameron via 2023-10-02 16:16 ` Jonathan Cameron 2023-10-03 11:44 ` Salil Mehta via 2023-10-03 11:44 ` Salil Mehta 2023-10-03 0:11 ` Gavin Shan 2023-10-03 11:45 ` Salil Mehta via 2023-10-03 11:45 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 08/10] physmem: Add helper function to destroy CPU AddressSpace Salil Mehta via 2023-10-02 16:20 ` Jonathan Cameron via 2023-10-02 16:20 ` Jonathan Cameron 2023-10-03 11:46 ` Salil Mehta via 2023-10-03 11:46 ` Salil Mehta 2023-10-03 1:36 ` Gavin Shan 2023-10-03 11:54 ` Salil Mehta via 2023-10-03 11:54 ` Salil Mehta 2023-10-04 10:48 ` Salil Mehta via 2023-10-04 10:48 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 09/10] gdbstub: Add helper function to unregister GDB register space Salil Mehta via 2023-10-03 3:16 ` Gavin Shan 2023-10-03 11:56 ` Salil Mehta via 2023-10-03 11:56 ` Salil Mehta 2023-09-30 0:19 ` [PATCH V2 10/10] target/arm/kvm: Write CPU state back to KVM on reset Salil Mehta via 2023-10-03 3:54 ` Gavin Shan
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