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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id v9-20020a17090331c900b0016796cdd802sm6207444ple.19.2022.06.09.12.49.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jun 2022 12:49:49 -0700 (PDT) Message-ID: Date: Thu, 9 Jun 2022 12:49:47 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v2 24/25] target/arm: Rearrange Secure PL1 test in arm_debug_target_el Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220607024734.541321-1-richard.henderson@linaro.org> <20220607024734.541321-25-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/9/22 09:53, Peter Maydell wrote: > On Tue, 7 Jun 2022 at 04:06, Richard Henderson > wrote: >> >> Not a bug, because arm_is_el2_enabled tests for secure, >> and SCR_EL3.EEL2 cannot be set for AArch32, however the >> ordering of the tests looks odd. Mirror the structure >> over in exception_target_el(). > > I think the code is following the ordering in the > DebugTarget() and DebugTargetFrom() pseudocode (or else some other > equivalent function in an older version of the Arm ARM...) Fair enough. > I think you're also relying on there being no secure EL2 > if EL3 is AArch32 (otherwise an exception from secure EL0 > might need to be routed to secure EL2, not EL3). Correct, though I don't imagine SEL2 will ever apply to A32. I'll drop the patch though. r~