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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>, qemu-devel@nongnu.org
Cc: Huacai Chen <chenhuacai@kernel.org>, Song Gao <gaosong@loongson.cn>
Subject: Re: [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS
Date: Mon, 3 Jun 2024 17:45:08 +0200	[thread overview]
Message-ID: <a3700c0c-889e-4bae-8a91-e374f8a5e03a@linaro.org> (raw)
In-Reply-To: <20240508-loongson3-ipi-v1-3-1a7b67704664@flygoat.com>

On 8/5/24 15:06, Jiaxun Yang wrote:
> Implement IOCSR address space get functions for MIPS/Loongson CPUs.
> 
> For MIPS/Loongson without IOCSR (i.e. Loongson-3A1000), get_cpu_iocsr_as
> will return as null, and send_ipi_data will fail with MEMTX_DECODE_ERROR,
> which matches expected behavior on hardware.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> I understand that there was a review comment stating that I shouldn't
> use TARGET_* macros in device drivers. But I still think this is the
> best way to handle architectural difference. There are many TARGET_*
> usages in hw/virtio for similiar purpose.
> ---
>   hw/intc/loongson_ipi.c | 39 ++++++++++++++++++++++++++++++---------
>   1 file changed, 30 insertions(+), 9 deletions(-)


>   static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr,
> @@ -56,18 +61,35 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr,
>       return MEMTX_OK;
>   }
>   
> -static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
> +static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
> +{
> +#ifdef TARGET_LOONGARCH64
> +    return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
> +#endif
> +#ifdef TARGET_MIPS
> +    if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
> +        return &MIPS_CPU(cpu)->env.iocsr.as;
> +    }
> +#endif
> +    return NULL;
> +}
> +
> +static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
>                             MemTxAttrs attrs)
>   {
>       int i, mask = 0, data = 0;
> +    AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);

LoongsonIPI should have an array of CPUState[] and MemoryRegion[].
(Or maybe add them to IPICore.)
Expose them as QOM link properties.

Caller wire them while creating the LoongsonIPI.
Then loongson_ipi_realize() resolves them once.
No need to call get_cpu_iocsr_as() and ipi_getcpu() for each MMIO
access IMO.

> +
> +    if (!iocsr_as) {
> +        return MEMTX_DECODE_ERROR;
> +    }



  parent reply	other threads:[~2024-06-03 15:46 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-08 13:06 [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support Jiaxun Yang
2024-05-08 13:06 ` [PATCH 1/5] hw/intc/loongarch_ipi: Remove pointless MAX_CPU check Jiaxun Yang
2024-05-08 16:22   ` Philippe Mathieu-Daudé
2024-05-08 13:06 ` [PATCH 2/5] hw/intc/loongarch_ipi: Rename as loongson_ipi Jiaxun Yang
2024-05-08 16:24   ` Philippe Mathieu-Daudé
2024-05-08 13:06 ` [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS Jiaxun Yang
2024-05-08 16:21   ` Philippe Mathieu-Daudé
2024-06-03 15:45   ` Philippe Mathieu-Daudé [this message]
2024-06-04 10:35     ` Jiaxun Yang
2024-06-04 12:37       ` gaosong
2024-05-08 13:06 ` [PATCH 4/5] hw/intc/loongson_ipi: Provide per core MMIO address spaces Jiaxun Yang
2024-05-08 13:06 ` [PATCH 5/5] hw/mips/loongson3_virt: Wire up loongson_ipi device Jiaxun Yang
2024-06-03 15:46   ` Philippe Mathieu-Daudé
2024-05-08 21:41 ` [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support Philippe Mathieu-Daudé
2024-05-16 10:53   ` Jiaxun Yang
2024-06-03 15:35     ` Philippe Mathieu-Daudé
2024-06-04 12:55       ` gaosong
2024-06-04 14:24         ` Philippe Mathieu-Daudé

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