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Mon, 03 Jun 2024 08:45:10 -0700 (PDT) Message-ID: Date: Mon, 3 Jun 2024 17:45:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS To: Jiaxun Yang , qemu-devel@nongnu.org Cc: Huacai Chen , Song Gao References: <20240508-loongson3-ipi-v1-0-1a7b67704664@flygoat.com> <20240508-loongson3-ipi-v1-3-1a7b67704664@flygoat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240508-loongson3-ipi-v1-3-1a7b67704664@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philmd@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/5/24 15:06, Jiaxun Yang wrote: > Implement IOCSR address space get functions for MIPS/Loongson CPUs. > > For MIPS/Loongson without IOCSR (i.e. Loongson-3A1000), get_cpu_iocsr_as > will return as null, and send_ipi_data will fail with MEMTX_DECODE_ERROR, > which matches expected behavior on hardware. > > Signed-off-by: Jiaxun Yang > --- > I understand that there was a review comment stating that I shouldn't > use TARGET_* macros in device drivers. But I still think this is the > best way to handle architectural difference. There are many TARGET_* > usages in hw/virtio for similiar purpose. > --- > hw/intc/loongson_ipi.c | 39 ++++++++++++++++++++++++++++++--------- > 1 file changed, 30 insertions(+), 9 deletions(-) > static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr, > @@ -56,18 +61,35 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr, > return MEMTX_OK; > } > > -static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr, > +static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) > +{ > +#ifdef TARGET_LOONGARCH64 > + return LOONGARCH_CPU(cpu)->env.address_space_iocsr; > +#endif > +#ifdef TARGET_MIPS > + if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { > + return &MIPS_CPU(cpu)->env.iocsr.as; > + } > +#endif > + return NULL; > +} > + > +static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, > MemTxAttrs attrs) > { > int i, mask = 0, data = 0; > + AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); LoongsonIPI should have an array of CPUState[] and MemoryRegion[]. (Or maybe add them to IPICore.) Expose them as QOM link properties. Caller wire them while creating the LoongsonIPI. Then loongson_ipi_realize() resolves them once. No need to call get_cpu_iocsr_as() and ipi_getcpu() for each MMIO access IMO. > + > + if (!iocsr_as) { > + return MEMTX_DECODE_ERROR; > + }