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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e1e85c905esm7388585a91.17.2024.10.07.09.24.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Oct 2024 09:24:03 -0700 (PDT) Message-ID: Date: Mon, 7 Oct 2024 09:24:01 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20241007025700.47259-1-zhiwei_liu@linux.alibaba.com> <20241007025700.47259-4-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241007025700.47259-4-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/6/24 19:56, LIU Zhiwei wrote: > +static void probe_frac_lmul(void) > +{ > + unsigned long vlmax[3]; > + > + for (int i = MO_8; i <= MO_64; ++i) { > + switch (i) { > + case MO_8: > + asm volatile( > + "vsetvli %0, zero, e8, mf2\n\t" > + "vsetvli %1, zero, e8, mf4\n\t" > + "vsetvli %2, zero, e8, mf8" > + : "=r"(vlmax[0]), "=r"(vlmax[1]), "=r"(vlmax[2]) > + ); > + break; > + case MO_16: > + asm volatile( > + "vsetvli %0, zero, e16, mf2\n\t" > + "vsetvli %1, zero, e16, mf4\n\t" > + "vsetvli %2, zero, e16, mf8" > + : "=r"(vlmax[0]), "=r"(vlmax[1]), "=r"(vlmax[2]) > + ); > + break; > + case MO_32: > + asm volatile( > + "vsetvli %0, zero, e32, mf2\n\t" > + "vsetvli %1, zero, e32, mf4\n\t" > + "vsetvli %2, zero, e32, mf8" > + : "=r"(vlmax[0]), "=r"(vlmax[1]), "=r"(vlmax[2]) > + ); > + break; > + case MO_64: > + asm volatile( > + "vsetvli %0, zero, e64, mf2\n\t" > + "vsetvli %1, zero, e64, mf4\n\t" > + "vsetvli %2, zero, e64, mf8" > + : "=r"(vlmax[0]), "=r"(vlmax[1]), "=r"(vlmax[2]) > + ); > + break; > + default: > + g_assert_not_reached(); > + } > + vaild_frac_lmul[i][1] = vlmax[0] != 0; > + vaild_frac_lmul[i][2] = vlmax[1] != 0; > + vaild_frac_lmul[i][3] = vlmax[2] != 0; > + } > } This fails to build on debian with default cflags: /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc: Assembler messages: /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2880: Error: unrecognized opcode `vsetvli a3,zero,e8,mf2', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2881: Error: unrecognized opcode `vsetvli a4,zero,e8,mf4', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2882: Error: unrecognized opcode `vsetvli a5,zero,e8,mf8', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2888: Error: unrecognized opcode `vsetvli a3,zero,e16,mf2', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2889: Error: unrecognized opcode `vsetvli a4,zero,e16,mf4', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2890: Error: unrecognized opcode `vsetvli a5,zero,e16,mf8', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2896: Error: unrecognized opcode `vsetvli a3,zero,e32,mf2', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2897: Error: unrecognized opcode `vsetvli a4,zero,e32,mf4', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2898: Error: unrecognized opcode `vsetvli a5,zero,e32,mf8', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2904: Error: unrecognized opcode `vsetvli a3,zero,e64,mf2', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2905: Error: unrecognized opcode `vsetvli a4,zero,e64,mf4', extension `v' or `zve64x' or `zve32x' required /home/rth/qemu/src/tcg/riscv/tcg-target.c.inc:2906: Error: unrecognized opcode `vsetvli a5,zero,e64,mf8', extension `v' or `zve64x' or `zve32x' required Rather than expanding this with a switch over immediate encodings, perhaps better feed encode_vtype() to the .insn encoding of vsetvl. > @@ -2160,6 +2483,7 @@ static void tcg_target_init(TCGContext *s) > tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; > break; > } > + probe_frac_lmul(); You need to avoid this call if the host does not support vectors. It occurs to me that, rather than caching valid_frac_lmul[][], we can pre-compute encode_vtype and lmul_eq_avl. It's not much of a savings within set_vtype(), but perhaps it is clearer. r~