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[60.242.98.186]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-203855dc2c6sm1662535ad.151.2024.08.21.17.25.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Aug 2024 17:25:41 -0700 (PDT) Message-ID: Date: Thu, 22 Aug 2024 10:25:33 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp To: Deepak Gupta , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com References: <20240821215014.3859190-1-debug@rivosinc.com> <20240821215014.3859190-6-debug@rivosinc.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240821215014.3859190-6-debug@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/22/24 07:50, Deepak Gupta wrote: > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9f08a67a9e..3a56bea8b9 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -133,6 +133,18 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, > flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); > } > > + if (cpu_get_fcfien(env)) { > + /* > + * For Forward CFI, only the expectation of a lpcll at s/lpcll/lpad/, though perhaps the whole paragraph could be simplified. We don't need to describe the mechanics of the extension, only what data defined by the spec are being copied into tb_flags. > @@ -1270,6 +1275,21 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > decode_opc(env, ctx, opcode16); > ctx->base.pc_next += ctx->cur_insn_len; > > + /* > + * instr decode of `lpad` should have lowered fcfi_lp_expected. > + * If not `lpad`, raise sw check exception. > + */ Perhaps better as If 'fcfi_lp_expected' is still true after processing the instruction, then we did not see an 'lpad' instruction, and must raise an exception. Insert code to raise the exception at the start of the insn; any other code the insn may have emitted will be deleted as dead code following the noreturn exception. r~