From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Anton Johansson <anjo@rev.ng>, qemu-devel@nongnu.org
Cc: philmd@linaro.org, richard.henderson@linaro.org,
alistair.francis@wdc.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh
Date: Thu, 2 Oct 2025 12:24:24 -0700 [thread overview]
Message-ID: <a3814f7c-cb74-438e-85ef-b580c10c6854@linaro.org> (raw)
In-Reply-To: <20251001073306.28573-9-anjo@rev.ng>
On 10/1/25 12:32 AM, Anton Johansson wrote:
> According to version 20250508 of the privileged specification,
> mhpmconter is a 64-bit register and mhpmcounterh refers to the top
> 32 bits of this register when XLEN == 32. No real advantage is
> gained by keeping them separate, and combining allows for slight
> simplification.
>
> Note, the cpu/pmu VMSTATE version is bumped breaking migration from
> older versions.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> target/riscv/cpu.h | 8 +--
> target/riscv/csr.c | 74 +++++++++++++--------------
> target/riscv/machine.c | 10 ++--
> target/riscv/pmu.c | 111 +++++++++++------------------------------
> 4 files changed, 70 insertions(+), 133 deletions(-)
>
...
> RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
> - bool upper_half, uint32_t ctr_idx)
> + bool upper_half, uint32_t ctr_idx)
> {
> PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> - target_ulong ctr_prev = upper_half ? counter->mhpmcounterh_prev :
> - counter->mhpmcounter_prev;
> - target_ulong ctr_val = upper_half ? counter->mhpmcounterh_val :
> - counter->mhpmcounter_val;
> + bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
> + int start = upper_half ? 32 : 0;
> + int length = rv32 ? 32 : 64;
> + uint64_t ctr_prev = extract64(counter->mhpmcounter_prev, start, length);
> + uint64_t ctr_val = extract64(counter->mhpmcounter_val, start, length);
> +
> + /* Ensure upper_half is only set for XLEN == 32 */
> + g_assert(rv32 || !upper_half);
An assert will be triggered by extract64 first if this happens.
static inline uint64_t extract64(uint64_t value, int start, int length)
{
assert(start >= 0 && length > 0 && length <= 64 - start);
Thus, you can move the assert before extract64 calls.
next prev parent reply other threads:[~2025-10-02 19:26 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 7:32 [PATCH v2 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 01/33] target/riscv: Use 32 bits for misa extensions Anton Johansson via
2025-10-01 7:34 ` Philippe Mathieu-Daudé
2025-10-02 1:56 ` Alistair Francis
2025-10-02 18:31 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 02/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-02 1:57 ` Alistair Francis
2025-10-02 18:31 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 03/33] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-01 7:38 ` Philippe Mathieu-Daudé
2025-10-01 8:28 ` Anton Johansson via
2025-10-02 18:34 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 04/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-02 18:50 ` Pierrick Bouvier
2025-10-02 23:34 ` Alistair Francis
2025-10-07 11:08 ` Anton Johansson via
2025-10-15 2:55 ` Alistair Francis
2025-10-15 9:58 ` Anton Johansson via
2025-10-16 4:01 ` Alistair Francis
2025-10-17 14:24 ` Anton Johansson via
2025-10-23 1:54 ` Alistair Francis
2025-10-01 7:32 ` [PATCH v2 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-01 7:39 ` Philippe Mathieu-Daudé
2025-10-02 19:09 ` Pierrick Bouvier
2025-10-02 23:52 ` Alistair Francis
2025-10-02 19:08 ` Pierrick Bouvier
2025-10-02 19:33 ` Pierrick Bouvier
2025-10-02 23:55 ` Alistair Francis
2025-10-07 11:29 ` Anton Johansson via
2025-10-14 11:25 ` Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-02 19:13 ` Pierrick Bouvier
2025-10-03 0:05 ` Alistair Francis
2025-10-01 7:32 ` [PATCH v2 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-02 19:14 ` Pierrick Bouvier
2025-10-03 0:06 ` Alistair Francis
2025-10-01 7:32 ` [PATCH v2 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-02 19:24 ` Pierrick Bouvier [this message]
2025-10-02 19:25 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-01 7:42 ` Philippe Mathieu-Daudé
2025-10-03 9:00 ` Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-02 19:42 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-02 19:54 ` Pierrick Bouvier
2025-10-03 12:43 ` Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-02 19:57 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-02 20:02 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-02 20:03 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-02 20:03 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-02 20:05 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-02 20:06 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-02 20:06 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-02 20:07 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-02 20:07 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-02 20:08 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-02 20:09 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-01 7:43 ` Philippe Mathieu-Daudé
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-01 7:43 ` Philippe Mathieu-Daudé
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-01 7:44 ` Philippe Mathieu-Daudé
2025-10-02 20:19 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-01 7:46 ` Philippe Mathieu-Daudé
2025-10-02 20:19 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-01 7:46 ` Philippe Mathieu-Daudé
2025-10-02 20:20 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-02 20:21 ` Pierrick Bouvier
2025-10-03 12:52 ` Anton Johansson via
2025-10-01 7:33 ` [PATCH v2 31/33] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-02 20:22 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-02 20:24 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
2025-10-01 7:49 ` Philippe Mathieu-Daudé
2025-10-03 12:57 ` Anton Johansson via
2025-10-02 20:23 ` Pierrick Bouvier
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