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Thu, 02 Oct 2025 12:24:25 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-28e8d126efesm28606815ad.30.2025.10.02.12.24.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 12:24:24 -0700 (PDT) Message-ID: Date: Thu, 2 Oct 2025 12:24:24 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Content-Language: en-US To: Anton Johansson , qemu-devel@nongnu.org Cc: philmd@linaro.org, richard.henderson@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com References: <20251001073306.28573-1-anjo@rev.ng> <20251001073306.28573-9-anjo@rev.ng> From: Pierrick Bouvier In-Reply-To: <20251001073306.28573-9-anjo@rev.ng> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/1/25 12:32 AM, Anton Johansson wrote: > According to version 20250508 of the privileged specification, > mhpmconter is a 64-bit register and mhpmcounterh refers to the top > 32 bits of this register when XLEN == 32. No real advantage is > gained by keeping them separate, and combining allows for slight > simplification. > > Note, the cpu/pmu VMSTATE version is bumped breaking migration from > older versions. > > Signed-off-by: Anton Johansson > --- > target/riscv/cpu.h | 8 +-- > target/riscv/csr.c | 74 +++++++++++++-------------- > target/riscv/machine.c | 10 ++-- > target/riscv/pmu.c | 111 +++++++++++------------------------------ > 4 files changed, 70 insertions(+), 133 deletions(-) > ... > RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, > - bool upper_half, uint32_t ctr_idx) > + bool upper_half, uint32_t ctr_idx) > { > PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; > - target_ulong ctr_prev = upper_half ? counter->mhpmcounterh_prev : > - counter->mhpmcounter_prev; > - target_ulong ctr_val = upper_half ? counter->mhpmcounterh_val : > - counter->mhpmcounter_val; > + bool rv32 = riscv_cpu_mxl(env) == MXL_RV32; > + int start = upper_half ? 32 : 0; > + int length = rv32 ? 32 : 64; > + uint64_t ctr_prev = extract64(counter->mhpmcounter_prev, start, length); > + uint64_t ctr_val = extract64(counter->mhpmcounter_val, start, length); > + > + /* Ensure upper_half is only set for XLEN == 32 */ > + g_assert(rv32 || !upper_half); An assert will be triggered by extract64 first if this happens. static inline uint64_t extract64(uint64_t value, int start, int length) { assert(start >= 0 && length > 0 && length <= 64 - start); Thus, you can move the assert before extract64 calls.