Re: [PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

[Richard Henderson <richard.henderson@linaro.org>]

On 7/2/24 01:10, ~liuxu wrote:
> +static bool gen_load_ld(DisasContext *ctx, arg_lb *a, MemOp memop, int flag)
> +{
> +    REQUIRE_ZCMLSD(ctx);
> +    REQUIRE_32BIT(ctx);
> +
> +    if (flag&&a->rd==0){
> +        return false;
> +    }
> +
> +    TCGv dest_low= dest_gpr(ctx, a->rd);
> +    TCGv addr = get_address(ctx, a->rs1, a->imm);
> +    tcg_gen_qemu_ld_tl(dest_low, addr, ctx->mem_idx, memop);
> +
> +    TCGv dest_high= dest_gpr(ctx, a->rd+1);
> +    tcg_gen_addi_tl(addr, addr, 32);
> +    tcg_gen_qemu_ld_tl(dest_high, addr, ctx->mem_idx, memop);
> +
> +    gen_set_gpr(ctx, a->rd, dest_low);
> +    gen_set_gpr(ctx, a->rd+1, dest_high);
> +
> +    return true;
> +}

You need to impliment this as one 64-bit load and split the data afterward with 
tcg_gen_extr_i64_tl().  That will also fix the incorrect increment that Alistair noted.


r~