From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 5/5] hw/intc/arm_gicv3: Provide ich_num_aprs()
Date: Sat, 7 May 2022 06:36:21 -0500 [thread overview]
Message-ID: <a3f0ba45-456a-bf76-2472-9727e94b2ba0@linaro.org> (raw)
In-Reply-To: <20220506162129.2896966-6-peter.maydell@linaro.org>
On 5/6/22 11:21, Peter Maydell wrote:
> @@ -145,11 +153,8 @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
> * in the ICH Active Priority Registers.
> */
> int i;
> - int aprmax = 1 << (cs->vprebits - 5);
>
> - assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
> -
> - for (i = 0; i < aprmax; i++) {
> + for (i = 0; i < ich_num_aprs(cs); i++) {
Better to retain the local variable for the loop bound.
r~
next prev parent reply other threads:[~2022-05-07 11:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-06 16:21 [PATCH 0/5] gicv3: Use right number of prio bits for the CPU Peter Maydell
2022-05-06 16:21 ` [PATCH 1/5] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 Peter Maydell
2022-05-06 16:21 ` [PATCH 2/5] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant Peter Maydell
2022-05-06 16:21 ` [PATCH 3/5] hw/intc/arm_gicv3: Support configurable number of physical priority bits Peter Maydell
2022-05-06 16:21 ` [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU Peter Maydell
2022-05-06 16:34 ` Peter Maydell
2022-05-07 7:49 ` Itaru Kitayama
2022-05-09 22:55 ` ishii.shuuichir
2022-05-10 9:09 ` Peter Maydell
2022-05-06 16:21 ` [PATCH 5/5] hw/intc/arm_gicv3: Provide ich_num_aprs() Peter Maydell
2022-05-07 11:36 ` Richard Henderson [this message]
2022-05-07 11:35 ` [PATCH 0/5] gicv3: Use right number of prio bits for the CPU Richard Henderson
2022-05-12 9:02 ` Peter Maydell
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