From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Bin Meng <bmeng@tinylab.org>, qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint()
Date: Mon, 6 Feb 2023 10:20:07 +0100 [thread overview]
Message-ID: <a441ba3c-a454-8680-bf52-9d71a0f9df7a@linaro.org> (raw)
In-Reply-To: <20230206085007.3618715-1-bmeng@tinylab.org>
On 6/2/23 09:50, Bin Meng wrote:
> There is no need to declare an intermediate "MachineState *ms".
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> hw/riscv/virt.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-02-06 9:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 8:50 [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint() Bin Meng
2023-02-06 9:20 ` Philippe Mathieu-Daudé [this message]
2023-02-06 22:21 ` Alistair Francis
2023-02-07 3:00 ` Alistair Francis
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