* [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint()
@ 2023-02-06 8:50 Bin Meng
2023-02-06 9:20 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Bin Meng @ 2023-02-06 8:50 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
There is no need to declare an intermediate "MachineState *ms".
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/virt.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a11b4b010..bdb6b93115 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1577,16 +1577,14 @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
static bool virt_get_aclint(Object *obj, Error **errp)
{
- MachineState *ms = MACHINE(obj);
- RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
return s->have_aclint;
}
static void virt_set_aclint(Object *obj, bool value, Error **errp)
{
- MachineState *ms = MACHINE(obj);
- RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
s->have_aclint = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint()
2023-02-06 8:50 [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint() Bin Meng
@ 2023-02-06 9:20 ` Philippe Mathieu-Daudé
2023-02-06 22:21 ` Alistair Francis
2023-02-07 3:00 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-06 9:20 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
On 6/2/23 09:50, Bin Meng wrote:
> There is no need to declare an intermediate "MachineState *ms".
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> hw/riscv/virt.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint()
2023-02-06 8:50 [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint() Bin Meng
2023-02-06 9:20 ` Philippe Mathieu-Daudé
@ 2023-02-06 22:21 ` Alistair Francis
2023-02-07 3:00 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-02-06 22:21 UTC (permalink / raw)
To: Bin Meng; +Cc: qemu-devel, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
On Mon, Feb 6, 2023 at 6:51 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> There is no need to declare an intermediate "MachineState *ms".
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/virt.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 4a11b4b010..bdb6b93115 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1577,16 +1577,14 @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
>
> static bool virt_get_aclint(Object *obj, Error **errp)
> {
> - MachineState *ms = MACHINE(obj);
> - RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> + RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
>
> return s->have_aclint;
> }
>
> static void virt_set_aclint(Object *obj, bool value, Error **errp)
> {
> - MachineState *ms = MACHINE(obj);
> - RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> + RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
>
> s->have_aclint = value;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint()
2023-02-06 8:50 [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint() Bin Meng
2023-02-06 9:20 ` Philippe Mathieu-Daudé
2023-02-06 22:21 ` Alistair Francis
@ 2023-02-07 3:00 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-02-07 3:00 UTC (permalink / raw)
To: Bin Meng; +Cc: qemu-devel, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
On Mon, Feb 6, 2023 at 6:51 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> There is no need to declare an intermediate "MachineState *ms".
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> hw/riscv/virt.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 4a11b4b010..bdb6b93115 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1577,16 +1577,14 @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
>
> static bool virt_get_aclint(Object *obj, Error **errp)
> {
> - MachineState *ms = MACHINE(obj);
> - RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> + RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
>
> return s->have_aclint;
> }
>
> static void virt_set_aclint(Object *obj, bool value, Error **errp)
> {
> - MachineState *ms = MACHINE(obj);
> - RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> + RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
>
> s->have_aclint = value;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-02-06 8:50 [PATCH] hw/riscv: virt: Simplify virt_{get,set}_aclint() Bin Meng
2023-02-06 9:20 ` Philippe Mathieu-Daudé
2023-02-06 22:21 ` Alistair Francis
2023-02-07 3:00 ` Alistair Francis
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