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From: Paolo Bonzini <pbonzini@redhat.com>
To: Laurent Vivier <laurent@vivier.eu>,
	Aurelien Jarno <aurelien@aurel32.net>
Cc: Richard Henderson <rth@twiddle.net>,
	qemu-devel@nongnu.org,
	John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Subject: Re: [Qemu-devel] [PATCH v2] target-sh4: add atomic tas
Date: Thu, 3 Nov 2016 17:18:07 +0100	[thread overview]
Message-ID: <a4464a3c-92d6-189b-aeee-5e267310bc6b@redhat.com> (raw)
In-Reply-To: <32960507-f61e-e3a1-76f3-74a755adb7e3@vivier.eu>



On 03/11/2016 16:35, Laurent Vivier wrote:
> Le 03/11/2016 à 16:32, Paolo Bonzini a écrit :
>>
>>
>> On 03/11/2016 15:07, Laurent Vivier wrote:
>>> Implement real atomic tas:
>>>
>>>     When (Rn) = 0, 1 -> T
>>>     Otherwise, 0 -> T
>>>     In both cases, 1 -> MSB of (Rn)
>>>
>>> using atomic_fetch_or_i32() and setcondi_i32().
>>>
>>> Tested with image from:
>>> http://wiki.qemu.org/download/sh-test-0.2.tar.bz2
>>>
>>> This image contains a "tas_test" that runs without
>>> error with this change.
>>>
>>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>>> ---
>>> v2:
>>> - don't use helper but atomic_fetch_or_i32
>>>   Thank you Paolo!
>>>
>>>  target-sh4/translate.c | 19 ++++++++-----------
>>>  1 file changed, 8 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
>>> index c89a147..1b83d59 100644
>>> --- a/target-sh4/translate.c
>>> +++ b/target-sh4/translate.c
>>> @@ -1640,18 +1640,15 @@ static void _decode_opc(DisasContext * ctx)
>>>  	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
>>>  	return;
>>>      case 0x401b:		/* tas.b @Rn */
>>> -	{
>>> -	    TCGv addr, val;
>>> -	    addr = tcg_temp_local_new();
>>> -	    tcg_gen_mov_i32(addr, REG(B11_8));
>>> -	    val = tcg_temp_local_new();
>>> -            tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
>>> +        {
>>> +            TCGv val = tcg_temp_new();
>>> +            TCGv msb = tcg_const_i32(0x80);
>>> +            tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), msb,
>>> +                                        ctx->memidx, MO_UB);
>>> +            tcg_temp_free(msb);
>>>              tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
>>> -	    tcg_gen_ori_i32(val, val, 0x80);
>>> -            tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
>>> -	    tcg_temp_free(val);
>>> -	    tcg_temp_free(addr);
>>> -	}
>>> +            tcg_temp_free(val);
>>> +        }
>>>  	return;
>>>      case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
>>>  	CHECK_FPU_ENABLED
>>>
>>
>> For 2.8?
> 
> Is it possible?

Well, tas_test "runs without error with this change", I suppose it fails
before?  In other words, is this patch enough to run multithreaded sh4
programs with qemu-user?

Paolo

  reply	other threads:[~2016-11-03 16:18 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-03 14:07 [Qemu-devel] [PATCH v2] target-sh4: add atomic tas Laurent Vivier
2016-11-03 14:53 ` Richard Henderson
2016-11-03 15:32 ` Paolo Bonzini
2016-11-03 15:35   ` Laurent Vivier
2016-11-03 16:18     ` Paolo Bonzini [this message]
2016-11-03 16:21       ` Laurent Vivier
2016-11-03 16:51         ` Laurent Vivier
2016-11-03 16:51         ` Richard Henderson
2016-11-03 17:52           ` Paolo Bonzini
2016-11-03 19:15             ` Richard Henderson
2016-11-04  9:23         ` John Paul Adrian Glaubitz
2016-11-04  9:43           ` John Paul Adrian Glaubitz
2016-11-04  9:53             ` Laurent Vivier
2016-11-04 10:00               ` John Paul Adrian Glaubitz
2016-11-04 10:13                 ` Paolo Bonzini
2016-11-04 10:16                   ` John Paul Adrian Glaubitz
2016-11-04 10:52                     ` Paolo Bonzini
2016-11-04  0:02 ` Aurelien Jarno

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