From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED756C7618F for ; Thu, 18 Jul 2019 22:46:15 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEB2C208C0 for ; Thu, 18 Jul 2019 22:46:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BEB2C208C0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hoFAE-0004eV-Sw for qemu-devel@archiver.kernel.org; Thu, 18 Jul 2019 18:46:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60124) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hoF9z-0003pu-SZ for qemu-devel@nongnu.org; Thu, 18 Jul 2019 18:46:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hoF9y-0006P7-ED for qemu-devel@nongnu.org; Thu, 18 Jul 2019 18:45:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40186) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hoF9r-0006J3-P7; Thu, 18 Jul 2019 18:45:52 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 890BE7FDE9; Thu, 18 Jul 2019 22:45:48 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-25.ams2.redhat.com [10.36.116.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id EE7915D719; Thu, 18 Jul 2019 22:45:43 +0000 (UTC) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20190718125928.20147-1-peter.maydell@linaro.org> From: Laszlo Ersek Message-ID: Date: Fri, 19 Jul 2019 00:45:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20190718125928.20147-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Thu, 18 Jul 2019 22:45:48 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-devel] [PATCH for-4.1] target/arm: Limit ID register assertions to TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 07/18/19 14:59, Peter Maydell wrote: > In arm_cpu_realizefn() we make several assertions about the values of > guest ID registers: > * if the CPU provides AArch32 v7VE or better it must advertise the > ARM_DIV feature > * if the CPU provides AArch32 A-profile v6 or better it must > advertise the Jazelle feature > > These are essentially consistency checks that our ID register > specifications in cpu.c didn't accidentally miss out a feature, > because increasingly the TCG emulation gates features on the values > in ID registers rather than using old-style checks of ARM_FEATURE_FOO > bits. > > Unfortunately, these asserts can cause problems if we're running KVM, > because in that case we don't control the values of the ID registers > -- we read them from the host kernel. In particular, if the host > kernel is older than 4.15 then it doesn't expose the ID registers via > the KVM_GET_ONE_REG ioctl, and we set up dummy values for some > registers and leave the rest at zero. (See the comment in > target/arm/kvm64.c kvm_arm_get_host_cpu_features().) This set of > dummy values is not sufficient to pass our assertions, and so on > those kernels running an AArch32 guest on AArch64 will assert. > > We could provide a more sophisticated set of dummy ID registers in > this case, but that still leaves the possibility of a host CPU which > reports bogus ID register values that would cause us to assert. It's > more robust to only do these ID register checks if we're using TCG, > as that is the only case where this is truly a QEMU code bug. > > Reported-by: Laszlo Ersek > Fixes: https://bugs.launchpad.net/qemu/+bug/1830864 > Signed-off-by: Peter Maydell > --- > Laszlo, would you mind testing this on your setup? I don't have > a system with an old enough kernel to trigger the assert. (The > change is pretty much a "has to work" one though :-)) 32-bit guest runs fine, with this patch applied to v4.1.0-rc1 :) Tested-by: Laszlo Ersek Thank you! Laszlo > > target/arm/cpu.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 1959467fdc8..9eb40ff755f 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1369,6 +1369,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > * There exist AArch64 cpus without AArch32 support. When KVM > * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. > * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. > + * As a general principle, we also do not make ID register > + * consistency checks anywhere unless using TCG, because only > + * for TCG would a consistency-check failure be a QEMU bug. > */ > if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { > no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); > @@ -1383,7 +1386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > * Presence of EL2 itself is ARM_FEATURE_EL2, and of the > * Security Extensions is ARM_FEATURE_EL3. > */ > - assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); > + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); > set_feature(env, ARM_FEATURE_LPAE); > set_feature(env, ARM_FEATURE_V7); > } > @@ -1409,7 +1412,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > if (arm_feature(env, ARM_FEATURE_V6)) { > set_feature(env, ARM_FEATURE_V5); > if (!arm_feature(env, ARM_FEATURE_M)) { > - assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); > + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); > set_feature(env, ARM_FEATURE_AUXCR); > } > } >