From: Richard Henderson <richard.henderson@linaro.org>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: "Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Greg Kurz" <groug@kaod.org>,
qemu-devel@nongnu.org
Subject: Re: [RFC PATCH 0/3] target/ppc: Change CR registers from i32 to tl
Date: Wed, 13 Sep 2023 15:29:51 -0700 [thread overview]
Message-ID: <a4773f18-f5c5-166a-ae06-5b14c1010964@linaro.org> (raw)
In-Reply-To: <20230913005814.413113-1-npiggin@gmail.com>
On 9/12/23 17:58, Nicholas Piggin wrote:
> This is a bit of churn so I might leave it for later in the cycle (or
> defer if we get a lot of other changes) since it's a relatively
> mechanical change. So don't spend time reviewing details, I'm just
> wondering about concept and general approach.
>
> I'm not sure the history of why these are 32-bit, maybe better code gen
> on 32-bit host emulating 64-bit? If so, that shouldn't be so important
> now that most people use 64-bit systems to develop and test with.
It was probably in order to save space, but I have no specific knowledge.
What does this do to the generated code? I suspect, without looking, that it doesn't
change things much at all on e.g. a ppc64 host, and for an x86_64 host merely changes the
types of some instructions (which, considering the rex64 encoding, might consume a few
more bytes).
r~
prev parent reply other threads:[~2023-09-13 22:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-13 0:58 [RFC PATCH 0/3] target/ppc: Change CR registers from i32 to tl Nicholas Piggin
2023-09-13 0:58 ` [RFC PATCH 1/3] " Nicholas Piggin
2023-09-13 0:58 ` [RFC PATCH 2/3] target/ppc: Use FP CR1 update helper more widely Nicholas Piggin
2023-09-13 6:19 ` Philippe Mathieu-Daudé
2023-09-13 0:58 ` [RFC PATCH 3/3] target/ppc: Optimise after CR register tl conversion Nicholas Piggin
2023-09-13 22:29 ` Richard Henderson [this message]
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