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Thu, 04 Nov 2021 11:43:37 -0700 (PDT) Subject: Re: [PATCH v3 23/29] bsd-user/arm/target_arch_signal.h: arm set_mcontext To: Warner Losh , qemu-devel@nongnu.org References: <20211104140536.42573-1-imp@bsdimp.com> <20211104140536.42573-24-imp@bsdimp.com> From: Richard Henderson Message-ID: Date: Thu, 4 Nov 2021 14:41:17 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211104140536.42573-24-imp@bsdimp.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.093, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stacey Son , qemu-trivial@nongnu.org, Kyle Evans , Michael Tokarev , Laurent Vivier , Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/4/21 10:05 AM, Warner Losh wrote: > + /* > + * Make sure T mode matches the PC's notion of thumb mode, although > + * FreeBSD lets the processor sort this out, so we may need remove > + * this check, or generate a signal... > + */ > + if (!!(tswap32(gr[TARGET_REG_PC]) & 1) != !!(cpsr & CPSR_T)) { > + return -TARGET_EINVAL; > + } I've had a read through the Arm ARM for "movs pc, lr", which is how swi_exit returns to userspace: CPSRWriteByInstr(SPSR[], '1111', TRUE); ... BranchWritePC(result); So the CPSR gets written first, which sets the T bit, and thus the result of CurrentInstrSet(), then BranchWritePC(bits(32) address) if CurrentInstrSet() == InstrSet_ARM then if ArchVersion() < 6 && address<1:0> != '00' then UNPREDICTABLE; BranchTo(address<31:2>:'00'); ... else BranchTo(address<31:1>:'0'); > + env->regs[15] = tswap32(gr[TARGET_REG_PC]); So this should mask the low 1 or 2 bits depending on cpsr & CPSR_T. r~