From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support
Date: Thu, 11 Jan 2018 07:31:00 -0800 [thread overview]
Message-ID: <a490bac7-e88b-cd4c-9922-f50461c591bc@linaro.org> (raw)
In-Reply-To: <1515637324-96034-7-git-send-email-mjc@sifive.com>
On 01/10/2018 06:21 PM, Michael Clark wrote:
> Helper routines for FPU instructions and NaN definitions.
>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> fpu/softfloat-specialize.h | 7 +-
> target/riscv/fpu_helper.c | 591 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 595 insertions(+), 3 deletions(-)
> create mode 100644 target/riscv/fpu_helper.c
It doesn't look like you have addressed any of my comments against v1 here.
r~
next prev parent reply other threads:[~2018-01-11 15:31 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-11 2:21 [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-11 14:32 ` Richard Henderson
2018-01-11 14:37 ` Richard Henderson
2018-01-11 17:55 ` Michael Clark
2018-01-12 3:03 ` Palmer Dabbelt
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler Michael Clark
2018-01-11 14:34 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers Michael Clark
2018-01-11 15:29 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support Michael Clark
2018-01-11 15:31 ` Richard Henderson [this message]
2018-01-11 18:09 ` Michael Clark
2018-01-11 20:01 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub Michael Clark
2018-01-11 15:31 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-11 15:47 ` Richard Henderson
2018-01-11 18:15 ` Michael Clark
2018-01-11 18:55 ` Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 12/21] RISC-V HART Array Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-11 9:10 ` Antony Pavlov
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-12 10:13 ` Antony Pavlov
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 " Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure Michael Clark
2018-01-11 14:05 ` Eric Blake
2018-01-11 18:43 ` Michael Clark
2018-02-04 21:15 ` Michael Clark
2018-01-11 3:01 ` [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 no-reply
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