From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 02/25] target/i386: rewrite flags writeback for ADCX/ADOX
Date: Sat, 8 Jun 2024 11:05:25 -0700 [thread overview]
Message-ID: <a4f062c9-249e-41cd-a2c1-1524b41c050c@linaro.org> (raw)
In-Reply-To: <20240608084113.2770363-3-pbonzini@redhat.com>
On 6/8/24 01:40, Paolo Bonzini wrote:
> Avoid using set_cc_op() in preparation for implementing APX; treat
> CC_OP_EFLAGS similar to the case where we have the "opposite" cc_op
> (CC_OP_ADOX for ADCX and CC_OP_ADCX for ADOX), except the resulting
> cc_op is not CC_OP_ADCOX. This is written easily as two "if"s, whose
> conditions are both false for CC_OP_EFLAGS, both true for CC_OP_ADCOX,
> and one each true for CC_OP_ADCX/ADOX.
>
> The new logic also makes it easy to drop usage of tmp0.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/cpu.h | 9 +++---
> target/i386/tcg/emit.c.inc | 61 ++++++++++++++++++++++----------------
> 2 files changed, 40 insertions(+), 30 deletions(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 8fe28b67e0f..ee873a0ed84 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1260,6 +1260,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
> /* Use a clearer name for this. */
> #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
>
> +#define CC_OP_HAS_EFLAGS(op) ((op) >= CC_OP_EFLAGS && (op) <= CC_OP_ADCOX)
> +
> /* Instead of computing the condition codes after each x86 instruction,
> * QEMU just stores one operand (called CC_SRC), the result
> * (called CC_DST) and the type of operation (called CC_OP). When the
> @@ -1270,6 +1272,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
> typedef enum {
> CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
> CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
> + CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
> + CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
> + CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
Comment for ADOX is (and was) wrong -- SRC2 = O.
That made review a bit confusing... :-)
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-06-08 18:06 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-08 8:40 [PATCH 00/25] target/i386: more progress towards new decoder Paolo Bonzini
2024-06-08 8:40 ` [PATCH 01/25] target/i386: remove CPUX86State argument from generator functions Paolo Bonzini
2024-06-08 14:47 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 02/25] target/i386: rewrite flags writeback for ADCX/ADOX Paolo Bonzini
2024-06-08 18:05 ` Richard Henderson [this message]
2024-06-08 8:40 ` [PATCH 03/25] target/i386: put BLS* input in T1, use generic flag writeback Paolo Bonzini
2024-06-08 18:07 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 04/25] target/i386: change X86_ENTRYr to use T0 Paolo Bonzini
2024-06-08 18:10 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 05/25] target/i386: change X86_ENTRYwr to use T0, use it for moves Paolo Bonzini
2024-06-08 18:13 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 06/25] target/i386: replace NoSeg special with NoLoadEA Paolo Bonzini
2024-06-08 18:16 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 07/25] target/i386: fix processing of intercept 0 (read CR0) Paolo Bonzini
2024-06-08 18:17 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 08/25] target/i386: convert MOV from/to CR and DR to new decoder Paolo Bonzini
2024-06-08 18:24 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 09/25] target/i386: fix bad sorting of entries in the 0F table Paolo Bonzini
2024-06-08 18:26 ` Richard Henderson
2024-06-08 8:40 ` [PATCH 10/25] target/i386: finish converting 0F AE to the new decoder Paolo Bonzini
2024-06-08 18:42 ` Richard Henderson
2024-10-21 1:49 ` Guenter Roeck
2024-10-21 6:57 ` Paolo Bonzini
2024-10-21 13:54 ` Guenter Roeck
2024-06-08 8:40 ` [PATCH 11/25] target/i386: replace read_crN helper with read_cr8 Paolo Bonzini
2024-06-08 18:45 ` Richard Henderson
2024-06-10 17:14 ` Paolo Bonzini
2024-06-08 8:41 ` [PATCH 12/25] target/i386: split X86_CHECK_prot into PE and VM86 checks Paolo Bonzini
2024-06-08 18:47 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 13/25] target/i386: convert non-grouped, helper-based 2-byte opcodes Paolo Bonzini
2024-06-08 19:03 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 14/25] target/i386: convert bit test instructions to new decoder Paolo Bonzini
2024-06-08 19:37 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 15/25] target/i386: pull load/writeback out of gen_shiftd_rm_T1 Paolo Bonzini
2024-06-08 19:39 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 16/25] target/i386: adapt gen_shift_count for SHLD/SHRD Paolo Bonzini
2024-06-08 19:42 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 17/25] target/i386: convert SHLD/SHRD to new decoder Paolo Bonzini
2024-06-08 19:47 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 18/25] target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT " Paolo Bonzini
2024-06-08 19:53 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 19/25] target/i386: convert XADD " Paolo Bonzini
2024-06-08 20:00 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 20/25] target/i386: convert CMPXCHG " Paolo Bonzini
2024-06-08 20:04 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 21/25] target/i386: decode address before going back to translate.c Paolo Bonzini
2024-06-08 20:13 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 22/25] target/i386: list instructions still in translate.c Paolo Bonzini
2024-06-08 20:14 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 23/25] target/i386: assert that cc_op* and pc_save are preserved Paolo Bonzini
2024-06-08 20:14 ` Richard Henderson
2024-06-08 8:41 ` [PATCH 24/25] target/i386: do not check PREFIX_LOCK in old-style decoder Paolo Bonzini
2024-06-08 20:15 ` Richard Henderson
2024-06-10 17:10 ` Paolo Bonzini
2024-06-08 8:41 ` [PATCH 25/25] target/i386: remove gen_ext_tl Paolo Bonzini
2024-06-08 20:17 ` Richard Henderson
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