Re: [PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field size

[Richard Henderson <richard.henderson@linaro.org>]

On 5/29/21 6:05 AM, Philippe Mathieu-Daudé wrote:
> Per the "MIPS® DSP Module for MIPS64 Architecture" manual (rev 3.02),
> Figure 5.12 "SPECIAL3 Encoding of APPEND/DAPPEND Instruction Sub-class"
> the byte position field ('bp') is 2 bits, not 3.

Rev 2.34 has 3 bits, not 2.

The mips32 version of balign, that uses 2 bits...  Are you sure you looked at 
the right instruction?  Because 3 bits makes most sense for this instruction 
with a 64-bit register size.


r~

> 
> Cc: Jia Liu <proljc@gmail.com>
> Fixes: 26690560240 ("target-mips: Add ASE DSP compare-pick instructions")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index c03a8ae1fed..e68647ce14c 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -23016,8 +23016,8 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
>               }
>               break;
>           case OPC_DBALIGN:
> -            sa &= 7;
> -            if (sa != 0 && sa != 2 && sa != 4) {
> +            sa &= 3;
> +            if (sa != 0 && sa != 2) {
>                   tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
>                   tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
>                   tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
>