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[50.78.183.178]) by smtp.gmail.com with ESMTPSA id s22sm2436816pfe.208.2021.05.30.08.33.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 May 2021 08:33:14 -0700 (PDT) Subject: Re: [PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field size To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20210529130520.1039274-1-f4bug@amsat.org> From: Richard Henderson Message-ID: Date: Sun, 30 May 2021 08:33:12 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210529130520.1039274-1-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.618, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aurelien Jarno , Jia Liu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/29/21 6:05 AM, Philippe Mathieu-Daudé wrote: > Per the "MIPS® DSP Module for MIPS64 Architecture" manual (rev 3.02), > Figure 5.12 "SPECIAL3 Encoding of APPEND/DAPPEND Instruction Sub-class" > the byte position field ('bp') is 2 bits, not 3. Rev 2.34 has 3 bits, not 2. The mips32 version of balign, that uses 2 bits... Are you sure you looked at the right instruction? Because 3 bits makes most sense for this instruction with a 64-bit register size. r~ > > Cc: Jia Liu > Fixes: 26690560240 ("target-mips: Add ASE DSP compare-pick instructions") > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/tcg/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c > index c03a8ae1fed..e68647ce14c 100644 > --- a/target/mips/tcg/translate.c > +++ b/target/mips/tcg/translate.c > @@ -23016,8 +23016,8 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, > } > break; > case OPC_DBALIGN: > - sa &= 7; > - if (sa != 0 && sa != 2 && sa != 4) { > + sa &= 3; > + if (sa != 0 && sa != 2) { > tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); > tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); > tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); >