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Wed, 23 Jul 2025 10:14:44 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b6b4ae8sm100469745ad.95.2025.07.23.10.14.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Jul 2025 10:14:44 -0700 (PDT) Message-ID: Date: Wed, 23 Jul 2025 10:14:42 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-10.1 6/6] target/arm: Fix LD1W, LD1D to 128-bit elements To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20250723165458.3509150-1-peter.maydell@linaro.org> <20250723165458.3509150-7-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250723165458.3509150-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/23/25 09:54, Peter Maydell wrote: > In our implementation of the SVE2p1 contiguous load to 128-bit > element insns such as LD1D (scalar plus scalar, single register), we > got the order of the arguments to the DO_LD1_2() macro wrong. Here > the first argument is the element size and the second is the memory > size, and the element size is always the same size or larger than > the memory size. > > For the 128-bit versions, we want to load either 32-bit or 64-bit > values from memory and extend them to the 128-bit vector element, but > were trying to load 128 bit values and then stuff them into 32-bit or > 64-bit vector elements. Correct the macro ordering. > > Fixes: fc5f060bcb7b ("target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1") > Signed-off-by: Peter Maydell > --- > target/arm/tcg/sve_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Double oops. Reviewed-by: Richard Henderson r~