From: Richard Henderson <rth@twiddle.net>
To: Sagar Karandikar <sagark@eecs.berkeley.edu>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, kbastian@mail.uni-paderborn.de
Subject: Re: [Qemu-devel] [PATCH 03/18] target-riscv: Add initialization for translation
Date: Mon, 26 Sep 2016 09:34:09 -0700 [thread overview]
Message-ID: <a542ec93-8690-1862-dd52-adaa56c0c24e@twiddle.net> (raw)
In-Reply-To: <c0ad80f0eec5fb80817ec1b4430b96d534852c87.1474886798.git.sagark@eecs.berkeley.edu>
On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> RISCVCPU *cpu_riscv_init(const char *cpu_model)
> {
> - return NULL;
> + RISCVCPU *cpu;
> + CPURISCVState *env;
> + const riscv_def_t *def;
> +
> + def = cpu_riscv_find_by_name(cpu_model);
> + if (!def) {
> + return NULL;
> + }
> + cpu = RISCV_CPU(object_new(TYPE_RISCV_CPU));
> + env = &cpu->env;
> + env->cpu_model = def;
> +
> + memset(env->csr, 0, 4096 * sizeof(target_ulong));
sizeof(env->csr)?
And besides that, doesn't this more properly belong in a reset function, where
that memset will already have been done?
> + env->priv = PRV_M;
> +
> + /* set mcpuid from def */
> + env->csr[CSR_MISA] = def->init_misa_reg;
> + object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
> +
> + /* fpu flags: */
> + set_default_nan_mode(1, &env->fp_status);
next prev parent reply other threads:[~2016-09-26 16:34 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-26 10:56 [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 01/18] target-riscv: Add RISC-V target stubs and Maintainer Sagar Karandikar
2016-09-26 19:06 ` Eric Blake
2016-09-26 10:56 ` [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/ Sagar Karandikar
2016-09-26 16:30 ` Richard Henderson
2016-09-26 21:50 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 03/18] target-riscv: Add initialization for translation Sagar Karandikar
2016-09-26 16:34 ` Richard Henderson [this message]
2016-09-26 10:56 ` [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode Sagar Karandikar
2016-09-26 16:49 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 05/18] target-riscv: Add Arithmetic instructions Sagar Karandikar
2016-09-26 17:31 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 06/18] target-riscv: Add JALR, Branch Instructions Sagar Karandikar
2016-09-26 18:28 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 07/18] target-riscv: Add Loads/Stores, FP Loads/Stores Sagar Karandikar
2016-09-26 20:44 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions Sagar Karandikar
2016-09-27 19:30 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions, Sagar Karandikar
2016-09-26 21:15 ` Richard Henderson
2016-09-27 19:20 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions Sagar Karandikar
2016-09-26 21:35 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 11/18] target-riscv: Add Double " Sagar Karandikar
2016-09-26 21:37 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions Sagar Karandikar
2016-09-26 12:21 ` Paolo Bonzini
2016-09-26 12:38 ` Bastian Koppelmann
2016-09-26 12:44 ` Paolo Bonzini
2016-09-27 18:12 ` Sagar Karandikar
2016-09-26 21:41 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 13/18] target-riscv: Add CSR read/write helpers Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 14/18] target-riscv: softmmu/address translation support Sagar Karandikar
2016-09-26 22:04 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 15/18] target-riscv: Interrupt Handling Sagar Karandikar
2016-09-26 22:07 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 16/18] target-riscv: Timer Support Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 17/18] target-riscv: Add support for Host-Target Interface (HTIF) Devices Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 18/18] target-riscv: Add generic test board, activate target Sagar Karandikar
2016-09-26 12:20 ` [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) Paolo Bonzini
2016-09-26 16:17 ` Richard Henderson
2016-09-26 16:20 ` Andreas Färber
2016-09-26 16:24 ` Paolo Bonzini
2016-09-26 16:35 ` Andreas Färber
2016-09-26 16:37 ` Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a542ec93-8690-1862-dd52-adaa56c0c24e@twiddle.net \
--to=rth@twiddle.net \
--cc=kbastian@mail.uni-paderborn.de \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).