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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, zhiwei_liu@linux.alibaba.com,
	wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
Date: Fri, 24 Feb 2023 08:44:32 -0300	[thread overview]
Message-ID: <a54a31d7-a85c-57eb-5d0b-d85e59348be3@ventanamicro.com> (raw)
In-Reply-To: <20230224040852.37109-3-liweiwei@iscas.ac.cn>



On 2/24/23 01:08, Weiwei Li wrote:
> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/csr.c | 13 +++++++++----
>   1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index feae23cab0..02cb2c2bb7 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
>           return ret;
>       }
>   
> -    *val = env->henvcfg;
> +    /*
> +     * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
> +     * henvcfg.stce is read_only 0 when menvcfg.stce = 0
> +     */
> +    *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
>       return RISCV_EXCP_NONE;
>   }
>   
> @@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
>       }
>   
>       if (riscv_cpu_mxl(env) == MXL_RV64) {
> -        mask |= HENVCFG_PBMTE | HENVCFG_STCE;
> +        mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
>       }
>   
>       env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
> @@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
>           return ret;
>       }
>   
> -    *val = env->henvcfg >> 32;
> +    *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
> +                            env->menvcfg)) >> 32;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
>                                     target_ulong val)
>   {
> -    uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
> +    uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
>       uint64_t valh = (uint64_t)val << 32;
>       RISCVException ret;
>   


  reply	other threads:[~2023-02-24 11:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-24  4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
2023-02-24  4:08 ` [PATCH 1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Weiwei Li
2023-02-24 11:40   ` Daniel Henrique Barboza
2023-02-24  4:08 ` [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Weiwei Li
2023-02-24 11:44   ` Daniel Henrique Barboza [this message]
2023-02-24 12:19   ` Andrew Jones
2023-02-24 12:36     ` liweiwei
2023-03-02  1:36       ` Palmer Dabbelt
2023-02-24  4:08 ` [PATCH 3/6] target/riscv: Add csr support for svadu Weiwei Li
2023-02-24 11:47   ` Daniel Henrique Barboza
2023-02-24  4:08 ` [PATCH 4/6] target/riscv: Add *envcfg.PBMTE related check in address translation Weiwei Li
2023-02-24 11:52   ` Daniel Henrique Barboza
2023-02-24  4:08 ` [PATCH 5/6] target/riscv: Add *envcfg.HADE " Weiwei Li
2023-02-24 11:53   ` Daniel Henrique Barboza
2023-02-24  4:08 ` [PATCH 6/6] target/riscv: Export Svadu property Weiwei Li
2023-02-24 11:56   ` Daniel Henrique Barboza
2023-03-02  1:36 ` [PATCH 0/6] target/riscv: Add support for Svadu extension Palmer Dabbelt

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