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Sun, 11 Apr 2021 08:12:14 -0700 (PDT) Received: from [192.168.1.11] ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id w124sm7347478pfb.73.2021.04.11.08.12.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 11 Apr 2021 08:12:14 -0700 (PDT) Subject: Re: [PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits To: Michael Rolnik , "Dr. David Alan Gilbert" References: <20210320220949.40965-1-mrolnik@gmail.com> <20210320220949.40965-2-mrolnik@gmail.com> From: Richard Henderson Message-ID: Date: Sun, 11 Apr 2021 08:12:11 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/10/21 10:24 AM, Michael Rolnik wrote: > Please review. The first 256b is i/o, the next 768b are ram. But having changed the page size, it should mean that the first 1k are now treated as i/o. We do have a path by which instructions in i/o pages can be executed. This happens on some ARM board setups during cold boot. But we do not save those translations, so they run much much slower than it should. But perhaps in the case of AVR, "much much slower" really isn't visible? In general, I think changing the page size is wrong. I also assume that migration is largely irrelevant to this target. r~ > > On Tue, Mar 23, 2021 at 10:28 PM Michael Rolnik > wrote: > > If I set TARGET_PAGE_BITS to 12 this *assert assert(v_l2_levels >= 0);* > will fail (page_table_config_init function) because > TARGET_PHYS_ADDR_SPACE_BITS is 24 bits, because AVR has 24 is the longest > pointer AVR has. I can set TARGET_PHYS_ADDR_SPACE_BITS to 32 and > TARGET_PAGE_BITS to 12 and everything will work fine. > What do you think? > > btw, wrote the original comment, you David referred to, when I did not know > that QEMU could map several regions to the same page, which is not true. > That's why I could change 8 to 10. > > On Tue, Mar 23, 2021 at 10:11 PM Michael Rolnik > wrote: > > how long? > > On Tue, Mar 23, 2021 at 2:46 PM Dr. David Alan Gilbert > > wrote: > > * Michael Rolnik (mrolnik@gmail.com ) wrote: > > Signed-off-by: Michael Rolnik > > > --- > >  target/avr/cpu-param.h | 8 +------- > >  target/avr/helper.c    | 2 -- > >  2 files changed, 1 insertion(+), 9 deletions(-) > > > > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h > > index 7ef4e7c679..9765a9d0db 100644 > > --- a/target/avr/cpu-param.h > > +++ b/target/avr/cpu-param.h > > @@ -22,13 +22,7 @@ > >  #define AVR_CPU_PARAM_H > > > >  #define TARGET_LONG_BITS 32 > > -/* > > - * TARGET_PAGE_BITS cannot be more than 8 bits because > > - * 1.  all IO registers occupy [0x0000 .. 0x00ff] address > range, and they > > - *     should be implemented as a device and not memory > > - * 2.  SRAM starts at the address 0x0100 > > I don't know AVR; but that seems to say why you can't make it any > larger > - how do you solve that? > > Dave > > > -#define TARGET_PAGE_BITS 8 > > +#define TARGET_PAGE_BITS 10 > >  #define TARGET_PHYS_ADDR_SPACE_BITS 24 > >  #define TARGET_VIRT_ADDR_SPACE_BITS 24 > >  #define NB_MMU_MODES 2 > > diff --git a/target/avr/helper.c b/target/avr/helper.c > > index 35e1019594..da658afed3 100644 > > --- a/target/avr/helper.c > > +++ b/target/avr/helper.c > > @@ -111,8 +111,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr > address, int size, > >      MemTxAttrs attrs = {}; > >      uint32_t paddr; > > > > -    address &= TARGET_PAGE_MASK; > > - > >      if (mmu_idx == MMU_CODE_IDX) { > >          /* access to code in flash */ > >          paddr = OFFSET_CODE + address; > > -- > > 2.25.1 > > > -- > Dr. David Alan Gilbert / dgilbert@redhat.com > / Manchester, UK > > > > -- > Best Regards, > Michael Rolnik > > > > -- > Best Regards, > Michael Rolnik > > > > -- > Best Regards, > Michael Rolnik