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Wed, 13 May 2020 09:21:38 +0000 (UTC) Subject: Re: [PATCH v4 3/4] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller To: Vikram Garhwal , qemu-devel@nongnu.org References: <1589314552-1375-1-git-send-email-fnu.vikram@xilinx.com> <1589314552-1375-4-git-send-email-fnu.vikram@xilinx.com> From: Thomas Huth Openpgp: preference=signencrypt Message-ID: Date: Wed, 13 May 2020 11:21:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <1589314552-1375-4-git-send-email-fnu.vikram@xilinx.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=205.139.110.61; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/13 01:56:38 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , francisco.iglesias@xilinx.com, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/05/2020 22.15, Vikram Garhwal wrote: > The QTests perform five tests on the Xilinx ZynqMP CAN controller: > Tests the CAN controller in loopback, sleep and snoop mode. > Tests filtering of incoming CAN messages. > > Signed-off-by: Vikram Garhwal > --- > tests/qtest/Makefile.include | 2 + > tests/qtest/xlnx-can-test.c | 367 +++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 369 insertions(+) > create mode 100644 tests/qtest/xlnx-can-test.c > > diff --git a/tests/qtest/Makefile.include b/tests/qtest/Makefile.include > index 9e5a51d..0996075 100644 > --- a/tests/qtest/Makefile.include > +++ b/tests/qtest/Makefile.include > @@ -136,6 +136,7 @@ check-qtest-aarch64-$(CONFIG_TPM_TIS_SYSBUS) += tpm-tis-device-swtpm-test > check-qtest-aarch64-y += numa-test > check-qtest-aarch64-y += boot-serial-test > check-qtest-aarch64-y += migration-test > +check-qtest-aarch64-y += xlnx-can-test > > # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional > ifneq ($(ARCH),arm) > @@ -265,6 +266,7 @@ tests/qtest/bios-tables-test$(EXESUF): tests/qtest/bios-tables-test.o \ > tests/qtest/boot-sector.o tests/qtest/acpi-utils.o $(libqos-obj-y) > tests/qtest/pxe-test$(EXESUF): tests/qtest/pxe-test.o tests/qtest/boot-sector.o $(libqos-obj-y) > tests/qtest/microbit-test$(EXESUF): tests/qtest/microbit-test.o > +tests/qtest/xlnx-can-test$(EXESUF): tests/qtest/xlnx-can-test.o > tests/qtest/m25p80-test$(EXESUF): tests/qtest/m25p80-test.o > tests/qtest/i440fx-test$(EXESUF): tests/qtest/i440fx-test.o $(libqos-pc-obj-y) > tests/qtest/q35-test$(EXESUF): tests/qtest/q35-test.o $(libqos-pc-obj-y) > diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c > new file mode 100644 > index 0000000..1307a2b > --- /dev/null > +++ b/tests/qtest/xlnx-can-test.c > @@ -0,0 +1,367 @@ > +/* > + * QTests for the Xilinx ZynqMP CAN controller. > + * > + * Copyright (c) 2020 Xilinx Inc. > + * > + * Written-by: Vikram Garhwal > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest.h" > + > +/* Xlnx-CAN base address. */ > +#define CAN0_BASE_ADDR 0xFF060000 > +#define CAN1_BASE_ADDR 0xFF070000 > + > +/* Register address in Xlnx-CAN. */ > +#define R_SRR_OFFSET 0x00 > +#define R_MSR_OFFSET 0x04 > +#define R_SR_OFFSET 0x18 > +#define R_ISR_OFFSET 0x1C > +#define R_ICR_OFFSET 0x24 > +#define R_TXID_OFFSET 0x30 > +#define R_TXDLC_OFFSET 0x34 > +#define R_TXDATA1_OFFSET 0x38 > +#define R_TXDATA2_OFFSET 0x3C > +#define R_RXID_OFFSET 0x50 > +#define R_RXDLC_OFFSET 0x54 > +#define R_RXDATA1_OFFSET 0x58 > +#define R_RXDATA2_OFFSET 0x5C > +#define R_AFR 0x60 > +#define R_AFMR1 0x64 > +#define R_AFIR1 0x68 > +#define R_AFMR2 0x6C > +#define R_AFIR2 0x70 > +#define R_AFMR3 0x74 > +#define R_AFIR3 0x78 > +#define R_AFMR4 0x7C > +#define R_AFIR4 0x80 > + > +/* CAN modes. */ > +#define CONFIG_MODE 0x00 > +#define NORMAL_MODE 0x00 > +#define LOOPBACK_MODE 0x02 > +#define SNOOP_MODE 0x04 > +#define SLEEP_MODE 0x01 > +#define ENABLE_CAN (1 << 1) > +#define STATUS_NORMAL_MODE (1 << 3) > +#define STATUS_LOOPBACK_MODE (1 << 1) > +#define STATUS_SNOOP_MODE (1 << 12) > +#define STATUS_SLEEP_MODE (1 << 2) > +#define ISR_TXOK (1 << 1) > +#define ISR_RXOK (1 << 4) > + > +static void match_rx_tx_data(uint32_t *buf_tx, uint32_t *buf_rx, > + uint8_t can_timestamp) > +{ > + uint16_t size = 0; > + uint8_t len = 4; > + > + while (size < len) { > + if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET) { > + g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp); > + } else { > + g_assert_cmpint(buf_rx[size], ==, buf_tx[size]); > + } > + > + size++; > + } > +} > + > +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) > +{ > + uint32_t int_status; > + > + /* Read the interrupt on CAN rx. */ > + int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; > + > + g_assert_cmpint(int_status, ==, ISR_RXOK); > + > + /* Read the RX register data for CAN. */ > + buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET); > + buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET); > + buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET); > + buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET); > + > + /* Clear the RX interrupt. */ > + qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK); > +} > + > +static void send_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_tx) > +{ > + uint32_t int_status; > + > + /* Write the TX register data for CAN. */ > + qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]); > + qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]); > + qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]); > + qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]); > + > + /* Read the interrupt on CAN for tx. */ > + int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK; > + > + g_assert_cmpint(int_status, ==, ISR_TXOK); > + > + /* Clear the interrupt for tx. */ > + qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK); > +} > + > +/* > + * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0 > + * initiate the data transfer to can-bus, CAN1 receives the data. Test compares > + * the data sent from CAN0 with received on CAN1. > + */ > +static void test_can_bus(void) > +{ > + uint32_t buf_tx[4] = {0xFF, 0x80000000, 0x12345678, 0x87654321}; > + uint32_t buf_rx[4] = {0x00, 0x00, 0x00, 0x00}; Just a matter of taste, but I'd add a space between the numbers and the curly braces. Anyway: Acked-by: Thomas Huth