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References: <cover.1542321076.git.alistair.francis@wdc.com>
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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <a5b5dda4-77df-6e28-509f-3a0ab696f390@linaro.org>
Date: Fri, 16 Nov 2018 09:26:30 +0100
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Subject: Re: [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the
 immediate encoders
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 11/15/18 11:35 PM, Alistair Francis wrote:
> +static int32_t encode_simm12(uint32_t imm)
> +{
> +    return ((imm << 20) >> 25) << 25 | ((imm << 27) >> 27) << 7;
> +}

I'm not fond of triple shifts like this, as it makes me count.
I'd be ok with a formulation like

    return ((imm & 0x1f) << 7) | ((imm & 0xfe) << (25 - 5));

but perhaps best as

    uint32_t ret = 0;
    ret = deposit32(ret, imm, 7, 5);
    ret = deposit32(ret, imm >> 5, 25, 7);

Similarly with encode_sbimm12, encode_uimm20 (which is a simple &), encode_ujimm12.


r~