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[88.26.246.243]) by smtp.gmail.com with ESMTPSA id u26sm2803794wrd.87.2019.10.17.08.48.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Oct 2019 08:48:38 -0700 (PDT) Subject: Re: [PATCH 7/8] hw/m68k/mcf5206.c: Switch to transaction-based ptimer API To: Peter Maydell , qemu-devel@nongnu.org References: <20191017132905.5604-1-peter.maydell@linaro.org> <20191017132905.5604-8-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 17 Oct 2019 17:48:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191017132905.5604-8-peter.maydell@linaro.org> Content-Language: en-US X-MC-Unique: VM41dRixM4K5KgHbiEyoig-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/17/19 3:29 PM, Peter Maydell wrote: > Switch the mcf5206 code away from bottom-half based ptimers to > the new transaction-based ptimer API. This just requires adding > begin/commit calls around the various places that modify the ptimer > state, and using the new ptimer_init() function to create the timer. >=20 > Signed-off-by: Peter Maydell > --- > hw/m68k/mcf5206.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) >=20 > diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c > index a49096367cb..c05401e0e50 100644 > --- a/hw/m68k/mcf5206.c > +++ b/hw/m68k/mcf5206.c > @@ -8,7 +8,6 @@ > =20 > #include "qemu/osdep.h" > #include "qemu/error-report.h" > -#include "qemu/main-loop.h" > #include "cpu.h" > #include "hw/hw.h" > #include "hw/irq.h" > @@ -57,6 +56,7 @@ static void m5206_timer_recalibrate(m5206_timer_state *= s) > int prescale; > int mode; > =20 > + ptimer_transaction_begin(s->timer); > ptimer_stop(s->timer); > =20 > if ((s->tmr & TMR_RST) =3D=3D 0) > @@ -78,6 +78,7 @@ static void m5206_timer_recalibrate(m5206_timer_state *= s) > ptimer_set_limit(s->timer, s->trr, 0); > =20 > ptimer_run(s->timer, 0); > + ptimer_transaction_commit(s->timer); > } > =20 > static void m5206_timer_trigger(void *opaque) > @@ -123,7 +124,9 @@ static void m5206_timer_write(m5206_timer_state *s, u= int32_t addr, uint32_t val) > s->tcr =3D val; > break; > case 0xc: > + ptimer_transaction_begin(s->timer); > ptimer_set_count(s->timer, val); > + ptimer_transaction_commit(s->timer); > break; > case 0x11: > s->ter &=3D ~val; > @@ -137,11 +140,9 @@ static void m5206_timer_write(m5206_timer_state *s, = uint32_t addr, uint32_t val) > static m5206_timer_state *m5206_timer_init(qemu_irq irq) > { > m5206_timer_state *s; > - QEMUBH *bh; > =20 > s =3D g_new0(m5206_timer_state, 1); > - bh =3D qemu_bh_new(m5206_timer_trigger, s); > - s->timer =3D ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); > + s->timer =3D ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_DEFAU= LT); > s->irq =3D irq; > m5206_timer_reset(s); > return s; >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9