* [PATCH 01/23] tests/tcg: update licenses to GPLv2 as intended
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 02/23] target/arm: Use GDBFeature for dynamic XML Alex Bennée
` (21 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
My default header template is GPLv3 but for QEMU code we really should
stick to GPLv2-or-later (allowing others to up-license it if they
wish). While this is test code we should still be consistent on the
source distribution.
I wrote all of this code so its not a problem. However there remains
one GPLv3 file left which is the crt0-tc2x.S for TriCore.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240215184036.214065-1-alex.bennee@linaro.org>
---
tests/tcg/aarch64/semicall.h | 4 ++--
tests/tcg/arm/semicall.h | 4 ++--
tests/tcg/multiarch/float_helpers.h | 4 ++--
tests/tcg/riscv64/semicall.h | 4 ++--
tests/tcg/multiarch/arm-compat-semi/semiconsole.c | 4 ++--
tests/tcg/multiarch/arm-compat-semi/semihosting.c | 4 ++--
tests/tcg/multiarch/float_convd.c | 4 ++--
tests/tcg/multiarch/float_convs.c | 4 ++--
tests/tcg/multiarch/float_madds.c | 4 ++--
tests/tcg/multiarch/libs/float_helpers.c | 4 ++--
tests/tcg/i386/system/boot.S | 6 +++---
tests/tcg/x86_64/system/boot.S | 6 +++---
12 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/tests/tcg/aarch64/semicall.h b/tests/tcg/aarch64/semicall.h
index 8a3fce35c5f..30d4de9a549 100644
--- a/tests/tcg/aarch64/semicall.h
+++ b/tests/tcg/aarch64/semicall.h
@@ -1,10 +1,10 @@
/*
* Semihosting Tests - AArch64 helper
*
- * Copyright (c) 2019
+ * Copyright (c) 2019, 2024
* Written by Alex Bennée <alex.bennee@linaro.org>
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
diff --git a/tests/tcg/arm/semicall.h b/tests/tcg/arm/semicall.h
index ad8ac51310b..624937c5577 100644
--- a/tests/tcg/arm/semicall.h
+++ b/tests/tcg/arm/semicall.h
@@ -1,10 +1,10 @@
/*
* Semihosting Tests - ARM Helper
*
- * Copyright (c) 2019
+ * Copyright (c) 2019, 2024
* Written by Alex Bennée <alex.bennee@linaro.org>
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
diff --git a/tests/tcg/multiarch/float_helpers.h b/tests/tcg/multiarch/float_helpers.h
index 309f3f4bf10..c42ebe64b9e 100644
--- a/tests/tcg/multiarch/float_helpers.h
+++ b/tests/tcg/multiarch/float_helpers.h
@@ -1,9 +1,9 @@
/*
* Common Float Helpers
*
- * Copyright (c) 2019 Linaro
+ * Copyright (c) 2019, 2024 Linaro
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <inttypes.h>
diff --git a/tests/tcg/riscv64/semicall.h b/tests/tcg/riscv64/semicall.h
index f8c88f32dc5..11d0650cb06 100644
--- a/tests/tcg/riscv64/semicall.h
+++ b/tests/tcg/riscv64/semicall.h
@@ -1,10 +1,10 @@
/*
* Semihosting Tests - RiscV64 Helper
*
- * Copyright (c) 2021
+ * Copyright (c) 2021, 2024
* Written by Alex Bennée <alex.bennee@linaro.org>
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
diff --git a/tests/tcg/multiarch/arm-compat-semi/semiconsole.c b/tests/tcg/multiarch/arm-compat-semi/semiconsole.c
index 1d82efc589d..1e2268f4b75 100644
--- a/tests/tcg/multiarch/arm-compat-semi/semiconsole.c
+++ b/tests/tcg/multiarch/arm-compat-semi/semiconsole.c
@@ -1,10 +1,10 @@
/*
* linux-user semihosting console
*
- * Copyright (c) 2019
+ * Copyright (c) 2024
* Written by Alex Bennée <alex.bennee@linaro.org>
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#define SYS_READC 0x07
diff --git a/tests/tcg/multiarch/arm-compat-semi/semihosting.c b/tests/tcg/multiarch/arm-compat-semi/semihosting.c
index 8627eee3cf7..f609c01341a 100644
--- a/tests/tcg/multiarch/arm-compat-semi/semihosting.c
+++ b/tests/tcg/multiarch/arm-compat-semi/semihosting.c
@@ -1,10 +1,10 @@
/*
* linux-user semihosting checks
*
- * Copyright (c) 2019
+ * Copyright (c) 2019, 2024
* Written by Alex Bennée <alex.bennee@linaro.org>
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#define SYS_WRITE0 0x04
diff --git a/tests/tcg/multiarch/float_convd.c b/tests/tcg/multiarch/float_convd.c
index 0a1f0f93dc5..58d7f8b4c58 100644
--- a/tests/tcg/multiarch/float_convd.c
+++ b/tests/tcg/multiarch/float_convd.c
@@ -1,9 +1,9 @@
/*
* Floating Point Convert Doubles to Various
*
- * Copyright (c) 2019 Linaro
+ * Copyright (c) 2019, 2024 Linaro
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <stdio.h>
diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_convs.c
index 2e4fa55324d..cb1fdd439e3 100644
--- a/tests/tcg/multiarch/float_convs.c
+++ b/tests/tcg/multiarch/float_convs.c
@@ -1,9 +1,9 @@
/*
* Floating Point Convert Single to Various
*
- * Copyright (c) 2019 Linaro
+ * Copyright (c) 2019, 2024 Linaro
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <stdio.h>
diff --git a/tests/tcg/multiarch/float_madds.c b/tests/tcg/multiarch/float_madds.c
index 4888f8641f4..a692e052d5b 100644
--- a/tests/tcg/multiarch/float_madds.c
+++ b/tests/tcg/multiarch/float_madds.c
@@ -1,9 +1,9 @@
/*
* Fused Multiply Add (Single)
*
- * Copyright (c) 2019 Linaro
+ * Copyright (c) 2019, 2024 Linaro
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <stdio.h>
diff --git a/tests/tcg/multiarch/libs/float_helpers.c b/tests/tcg/multiarch/libs/float_helpers.c
index 4e68d2b6598..fad5fc98933 100644
--- a/tests/tcg/multiarch/libs/float_helpers.c
+++ b/tests/tcg/multiarch/libs/float_helpers.c
@@ -5,9 +5,9 @@
* floating point constants useful for exercising the edge cases in
* floating point tests.
*
- * Copyright (c) 2019 Linaro
+ * Copyright (c) 2019, 2024 Linaro
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
/* we want additional float type definitions */
diff --git a/tests/tcg/i386/system/boot.S b/tests/tcg/i386/system/boot.S
index 9e8920cbfe0..28902c400d8 100644
--- a/tests/tcg/i386/system/boot.S
+++ b/tests/tcg/i386/system/boot.S
@@ -2,12 +2,12 @@
* i386 boot code, based on qemu-bmibug.
*
* Copyright 2019 Doug Gale
- * Copyright 2019 Linaro
+ * Copyright 2019, 2024 Linaro
*
- * This work is licensed under the terms of the GNU GPL, version 3 or later.
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
.section .head
diff --git a/tests/tcg/x86_64/system/boot.S b/tests/tcg/x86_64/system/boot.S
index dac9bd534d7..7213aec63b2 100644
--- a/tests/tcg/x86_64/system/boot.S
+++ b/tests/tcg/x86_64/system/boot.S
@@ -1,16 +1,16 @@
/*
* x86_64 boot and support code
*
- * Copyright 2019 Linaro
+ * Copyright 2019, 2024 Linaro
*
- * This work is licensed under the terms of the GNU GPL, version 3 or later.
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
* Unlike the i386 version we instead use Xen's PVHVM booting header
* which should drop us automatically into 32 bit mode ready to go. I've
* nabbed bits of the Linux kernel setup to achieve this.
*
- * SPDX-License-Identifier: GPL-3.0-or-later
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
.section .head
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 02/23] target/arm: Use GDBFeature for dynamic XML
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
2024-02-16 16:30 ` [PATCH 01/23] tests/tcg: update licenses to GPLv2 as intended Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 03/23] target/ppc: " Alex Bennée
` (20 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240103173349.398526-27-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-1-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu.h | 21 +++---
target/arm/internals.h | 2 +-
target/arm/gdbstub.c | 142 ++++++++++++++++++++---------------------
target/arm/gdbstub64.c | 95 +++++++++++++--------------
4 files changed, 123 insertions(+), 137 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 63f31e0d984..508a9c1e0d6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,7 @@
#include "hw/registerfields.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "exec/gdbstub.h"
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
@@ -117,23 +118,21 @@
*/
/**
- * DynamicGDBXMLInfo:
- * @desc: Contains the XML descriptions.
- * @num: Number of the registers in this XML seen by GDB.
+ * DynamicGDBFeatureInfo:
+ * @desc: Contains the feature descriptions.
* @data: A union with data specific to the set of registers
* @cpregs_keys: Array that contains the corresponding Key of
* a given cpreg with the same order of the cpreg
* in the XML description.
*/
-typedef struct DynamicGDBXMLInfo {
- char *desc;
- int num;
+typedef struct DynamicGDBFeatureInfo {
+ GDBFeature desc;
union {
struct {
uint32_t *keys;
} cpregs;
} data;
-} DynamicGDBXMLInfo;
+} DynamicGDBFeatureInfo;
/* CPU state for each instance of a generic timer (in cp15 c14) */
typedef struct ARMGenericTimer {
@@ -855,10 +854,10 @@ struct ArchCPU {
uint64_t *cpreg_vmstate_values;
int32_t cpreg_vmstate_array_len;
- DynamicGDBXMLInfo dyn_sysreg_xml;
- DynamicGDBXMLInfo dyn_svereg_xml;
- DynamicGDBXMLInfo dyn_m_systemreg_xml;
- DynamicGDBXMLInfo dyn_m_secextreg_xml;
+ DynamicGDBFeatureInfo dyn_sysreg_feature;
+ DynamicGDBFeatureInfo dyn_svereg_feature;
+ DynamicGDBFeatureInfo dyn_m_systemreg_feature;
+ DynamicGDBFeatureInfo dyn_m_secextreg_feature;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 50bff445494..05eb9daac7d 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1451,7 +1451,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
}
#ifdef TARGET_AARCH64
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
+GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 28f546a5ff9..5949adfb31a 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -26,11 +26,11 @@
#include "cpu-features.h"
#include "cpregs.h"
-typedef struct RegisterSysregXmlParam {
+typedef struct RegisterSysregFeatureParam {
CPUState *cs;
- GString *s;
+ GDBFeatureBuilder builder;
int n;
-} RegisterSysregXmlParam;
+} RegisterSysregFeatureParam;
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
whatever the target description contains. Due to a historical mishap
@@ -216,7 +216,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
const ARMCPRegInfo *ri;
uint32_t key;
- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
+ key = cpu->dyn_sysreg_feature.data.cpregs.keys[reg];
ri = get_arm_cp_reginfo(cpu->cp_regs, key);
if (ri) {
if (cpreg_field_is_64bit(ri)) {
@@ -233,34 +233,32 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
-static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
+static void arm_gen_one_feature_sysreg(GDBFeatureBuilder *builder,
+ DynamicGDBFeatureInfo *dyn_feature,
ARMCPRegInfo *ri, uint32_t ri_key,
- int bitsize, int regnum)
+ int bitsize, int n)
{
- g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
- g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
- g_string_append_printf(s, " regnum=\"%d\"", regnum);
- g_string_append_printf(s, " group=\"cp_regs\"/>");
- dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
- dyn_xml->num++;
+ gdb_feature_builder_append_reg(builder, ri->name, bitsize, n,
+ "int", "cp_regs");
+
+ dyn_feature->data.cpregs.keys[n] = ri_key;
}
-static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
- gpointer p)
+static void arm_register_sysreg_for_feature(gpointer key, gpointer value,
+ gpointer p)
{
uint32_t ri_key = (uintptr_t)key;
ARMCPRegInfo *ri = value;
- RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
- GString *s = param->s;
+ RegisterSysregFeatureParam *param = p;
ARMCPU *cpu = ARM_CPU(param->cs);
CPUARMState *env = &cpu->env;
- DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;
+ DynamicGDBFeatureInfo *dyn_feature = &cpu->dyn_sysreg_feature;
if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
if (ri->state == ARM_CP_STATE_AA64) {
- arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
- param->n++);
+ arm_gen_one_feature_sysreg(¶m->builder, dyn_feature,
+ ri, ri_key, 64, param->n++);
}
} else {
if (ri->state == ARM_CP_STATE_AA32) {
@@ -269,32 +267,32 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
return;
}
if (ri->type & ARM_CP_64BIT) {
- arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
- param->n++);
+ arm_gen_one_feature_sysreg(¶m->builder, dyn_feature,
+ ri, ri_key, 64, param->n++);
} else {
- arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
- param->n++);
+ arm_gen_one_feature_sysreg(¶m->builder, dyn_feature,
+ ri, ri_key, 32, param->n++);
}
}
}
}
}
-static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
+static GDBFeature *arm_gen_dynamic_sysreg_feature(CPUState *cs, int base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
- GString *s = g_string_new(NULL);
- RegisterSysregXmlParam param = {cs, s, base_reg};
-
- cpu->dyn_sysreg_xml.num = 0;
- cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
- g_string_printf(s, "<?xml version=\"1.0\"?>");
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
- g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
- g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m);
- g_string_append_printf(s, "</feature>");
- cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
- return cpu->dyn_sysreg_xml.num;
+ RegisterSysregFeatureParam param = {cs};
+ gsize num_regs = g_hash_table_size(cpu->cp_regs);
+
+ gdb_feature_builder_init(¶m.builder,
+ &cpu->dyn_sysreg_feature.desc,
+ "org.qemu.gdb.arm.sys.regs",
+ "system-registers.xml",
+ base_reg);
+ cpu->dyn_sysreg_feature.data.cpregs.keys = g_new(uint32_t, num_regs);
+ g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_feature, ¶m);
+ gdb_feature_builder_end(¶m.builder);
+ return &cpu->dyn_sysreg_feature.desc;
}
#ifdef CONFIG_TCG
@@ -386,31 +384,29 @@ static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
return 0; /* TODO */
}
-static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
+static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs,
+ int base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
- GString *s = g_string_new(NULL);
- int base_reg = orig_base_reg;
+ GDBFeatureBuilder builder;
+ int reg = 0;
int i;
- g_string_printf(s, "<?xml version=\"1.0\"?>");
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
+ gdb_feature_builder_init(&builder, &cpu->dyn_m_systemreg_feature.desc,
+ "org.gnu.gdb.arm.m-system", "arm-m-system.xml",
+ base_reg);
for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
if (arm_feature(env, m_sysreg_def[i].feature)) {
- g_string_append_printf(s,
- "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
- m_sysreg_def[i].name, base_reg++);
+ gdb_feature_builder_append_reg(&builder, m_sysreg_def[i].name, 32,
+ reg++, "int", NULL);
}
}
- g_string_append_printf(s, "</feature>");
- cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
- cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
+ gdb_feature_builder_end(&builder);
- return cpu->dyn_m_systemreg_xml.num;
+ return &cpu->dyn_m_systemreg_feature.desc;
}
#ifndef CONFIG_USER_ONLY
@@ -428,31 +424,31 @@ static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
return 0; /* TODO */
}
-static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
+static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs,
+ int base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
- GString *s = g_string_new(NULL);
- int base_reg = orig_base_reg;
+ GDBFeatureBuilder builder;
+ char *name;
+ int reg = 0;
int i;
- g_string_printf(s, "<?xml version=\"1.0\"?>");
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
+ gdb_feature_builder_init(&builder, &cpu->dyn_m_secextreg_feature.desc,
+ "org.gnu.gdb.arm.secext", "arm-m-secext.xml",
+ base_reg);
for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
- g_string_append_printf(s,
- "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
- m_sysreg_def[i].name, base_reg++);
- g_string_append_printf(s,
- "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
- m_sysreg_def[i].name, base_reg++);
+ name = g_strconcat(m_sysreg_def[i].name, "_ns", NULL);
+ gdb_feature_builder_append_reg(&builder, name, 32, reg++,
+ "int", NULL);
+ name = g_strconcat(m_sysreg_def[i].name, "_s", NULL);
+ gdb_feature_builder_append_reg(&builder, name, 32, reg++,
+ "int", NULL);
}
- g_string_append_printf(s, "</feature>");
- cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
- cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
+ gdb_feature_builder_end(&builder);
- return cpu->dyn_m_secextreg_xml.num;
+ return &cpu->dyn_m_secextreg_feature.desc;
}
#endif
#endif /* CONFIG_TCG */
@@ -462,14 +458,14 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
ARMCPU *cpu = ARM_CPU(cs);
if (strcmp(xmlname, "system-registers.xml") == 0) {
- return cpu->dyn_sysreg_xml.desc;
+ return cpu->dyn_sysreg_feature.desc.xml;
} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
- return cpu->dyn_svereg_xml.desc;
+ return cpu->dyn_svereg_feature.desc.xml;
} else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
- return cpu->dyn_m_systemreg_xml.desc;
+ return cpu->dyn_m_systemreg_feature.desc.xml;
#ifndef CONFIG_USER_ONLY
} else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
- return cpu->dyn_m_secextreg_xml.desc;
+ return cpu->dyn_m_secextreg_feature.desc.xml;
#endif
}
return NULL;
@@ -487,7 +483,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
*/
#ifdef TARGET_AARCH64
if (isar_feature_aa64_sve(&cpu->isar)) {
- int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
+ int nreg = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs)->num_regs;
gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
aarch64_gdb_set_sve_reg, nreg,
"sve-registers.xml", 0);
@@ -533,20 +529,20 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1, "arm-m-profile-mve.xml", 0);
}
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
- arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
+ arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs)->num_regs,
"system-registers.xml", 0);
#ifdef CONFIG_TCG
if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
- arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
+ arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num_regs,
"arm-m-system.xml", 0);
#ifndef CONFIG_USER_ONLY
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
- arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
+ arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)->num_regs,
"arm-m-secext.xml", 0);
}
#endif
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index d7b79a6589b..5286d5c6043 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -247,7 +247,7 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
-static void output_vector_union_type(GString *s, int reg_width,
+static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_width,
const char *name)
{
struct TypeSize {
@@ -282,10 +282,10 @@ static void output_vector_union_type(GString *s, int reg_width,
/* First define types and totals in a whole VL */
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
- g_string_append_printf(s,
- "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
- name, vec_lanes[i].sz, vec_lanes[i].suffix,
- vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
+ gdb_feature_builder_append_tag(
+ builder, "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
+ name, vec_lanes[i].sz, vec_lanes[i].suffix,
+ vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
}
/*
@@ -296,86 +296,77 @@ static void output_vector_union_type(GString *s, int reg_width,
for (i = 0; i < ARRAY_SIZE(suf); i++) {
int bits = 8 << i;
- g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
+ gdb_feature_builder_append_tag(builder, "<union id=\"%sn%c\">",
+ name, suf[i]);
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
if (vec_lanes[j].size == bits) {
- g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
- vec_lanes[j].suffix, name,
- vec_lanes[j].sz, vec_lanes[j].suffix);
+ gdb_feature_builder_append_tag(
+ builder, "<field name=\"%c\" type=\"%s%c%c\"/>",
+ vec_lanes[j].suffix, name,
+ vec_lanes[j].sz, vec_lanes[j].suffix);
}
}
- g_string_append(s, "</union>");
+ gdb_feature_builder_append_tag(builder, "</union>");
}
/* And now the final union of unions */
- g_string_append_printf(s, "<union id=\"%s\">", name);
+ gdb_feature_builder_append_tag(builder, "<union id=\"%s\">", name);
for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
- g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
- suf[i], name, suf[i]);
+ gdb_feature_builder_append_tag(builder,
+ "<field name=\"%c\" type=\"%sn%c\"/>",
+ suf[i], name, suf[i]);
}
- g_string_append(s, "</union>");
+ gdb_feature_builder_append_tag(builder, "</union>");
}
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
- GString *s = g_string_new(NULL);
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
int reg_width = cpu->sve_max_vq * 128;
int pred_width = cpu->sve_max_vq * 16;
- int base_reg = orig_base_reg;
+ GDBFeatureBuilder builder;
+ char *name;
+ int reg = 0;
int i;
- g_string_printf(s, "<?xml version=\"1.0\"?>");
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+ gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc,
+ "org.gnu.gdb.aarch64.sve", "sve-registers.xml",
+ base_reg);
/* Create the vector union type. */
- output_vector_union_type(s, reg_width, "svev");
+ output_vector_union_type(&builder, reg_width, "svev");
/* Create the predicate vector type. */
- g_string_append_printf(s,
- "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
- pred_width / 8);
+ gdb_feature_builder_append_tag(
+ &builder, "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+ pred_width / 8);
/* Define the vector registers. */
for (i = 0; i < 32; i++) {
- g_string_append_printf(s,
- "<reg name=\"z%d\" bitsize=\"%d\""
- " regnum=\"%d\" type=\"svev\"/>",
- i, reg_width, base_reg++);
+ name = g_strdup_printf("z%d", i);
+ gdb_feature_builder_append_reg(&builder, name, reg_width, reg++,
+ "svev", NULL);
}
/* fpscr & status registers */
- g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
- " regnum=\"%d\" group=\"float\""
- " type=\"int\"/>", base_reg++);
- g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
- " regnum=\"%d\" group=\"float\""
- " type=\"int\"/>", base_reg++);
+ gdb_feature_builder_append_reg(&builder, "fpsr", 32, reg++,
+ "int", "float");
+ gdb_feature_builder_append_reg(&builder, "fpcr", 32, reg++,
+ "int", "float");
/* Define the predicate registers. */
for (i = 0; i < 16; i++) {
- g_string_append_printf(s,
- "<reg name=\"p%d\" bitsize=\"%d\""
- " regnum=\"%d\" type=\"svep\"/>",
- i, pred_width, base_reg++);
+ name = g_strdup_printf("p%d", i);
+ gdb_feature_builder_append_reg(&builder, name, pred_width, reg++,
+ "svep", NULL);
}
- g_string_append_printf(s,
- "<reg name=\"ffr\" bitsize=\"%d\""
- " regnum=\"%d\" group=\"vector\""
- " type=\"svep\"/>",
- pred_width, base_reg++);
+ gdb_feature_builder_append_reg(&builder, "ffr", pred_width, reg++,
+ "svep", "vector");
/* Define the vector length pseudo-register. */
- g_string_append_printf(s,
- "<reg name=\"vg\" bitsize=\"64\""
- " regnum=\"%d\" type=\"int\"/>",
- base_reg++);
+ gdb_feature_builder_append_reg(&builder, "vg", 64, reg++, "int", NULL);
- g_string_append_printf(s, "</feature>");
+ gdb_feature_builder_end(&builder);
- info->desc = g_string_free(s, false);
- info->num = base_reg - orig_base_reg;
- return info->num;
+ return &cpu->dyn_svereg_feature.desc;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 03/23] target/ppc: Use GDBFeature for dynamic XML
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
2024-02-16 16:30 ` [PATCH 01/23] tests/tcg: update licenses to GPLv2 as intended Alex Bennée
2024-02-16 16:30 ` [PATCH 02/23] target/arm: Use GDBFeature for dynamic XML Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 04/23] target/riscv: " Alex Bennée
` (19 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240103173349.398526-28-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-2-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/ppc/cpu-qom.h | 1 +
target/ppc/cpu.h | 4 +---
target/ppc/cpu_init.c | 4 ----
target/ppc/gdbstub.c | 51 ++++++++++++++++---------------------------
4 files changed, 21 insertions(+), 39 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 0241609efef..8247fa23367 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -20,6 +20,7 @@
#ifndef QEMU_PPC_CPU_QOM_H
#define QEMU_PPC_CPU_QOM_H
+#include "exec/gdbstub.h"
#include "hw/core/cpu.h"
#ifdef TARGET_PPC64
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a44de22ca4a..200652e2c87 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1471,8 +1471,7 @@ struct PowerPCCPUClass {
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
#ifndef CONFIG_USER_ONLY
- unsigned int gdb_num_sprs;
- const char *gdb_spr_xml;
+ GDBFeature gdb_spr;
#endif
const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
@@ -1525,7 +1524,6 @@ int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
#ifndef CONFIG_USER_ONLY
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
#endif
int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9931372a08a..4f6903d3f16 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6682,10 +6682,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
(*pcc->init_proc)(env);
-#if !defined(CONFIG_USER_ONLY)
- ppc_gdb_gen_spr_xml(cpu);
-#endif
-
/* MSR bits & flags consistency checks */
if (env->msr_mask & (1 << 25)) {
switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index ec5731e5d67..e3be3dbd109 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -300,15 +300,23 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
}
#ifndef CONFIG_USER_ONLY
-void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
+static void gdb_gen_spr_feature(CPUState *cs)
{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- GString *xml;
- char *spr_name;
+ GDBFeatureBuilder builder;
unsigned int num_regs = 0;
int i;
+ if (pcc->gdb_spr.xml) {
+ return;
+ }
+
+ gdb_feature_builder_init(&builder, &pcc->gdb_spr,
+ "org.qemu.power.spr", "power-spr.xml",
+ cs->gdb_num_regs);
+
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
ppc_spr_t *spr = &env->spr_cb[i];
@@ -326,35 +334,13 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
*/
spr->gdb_id = num_regs;
num_regs++;
- }
-
- if (pcc->gdb_spr_xml) {
- return;
- }
- xml = g_string_new("<?xml version=\"1.0\"?>");
- g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
- g_string_append(xml, "<feature name=\"org.qemu.power.spr\">");
-
- for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
- ppc_spr_t *spr = &env->spr_cb[i];
-
- if (!spr->name) {
- continue;
- }
-
- spr_name = g_ascii_strdown(spr->name, -1);
- g_string_append_printf(xml, "<reg name=\"%s\"", spr_name);
- g_free(spr_name);
-
- g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
- g_string_append(xml, " group=\"spr\"/>");
+ gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
+ TARGET_LONG_BITS, num_regs,
+ "int", "spr");
}
- g_string_append(xml, "</feature>");
-
- pcc->gdb_num_sprs = num_regs;
- pcc->gdb_spr_xml = g_string_free(xml, false);
+ gdb_feature_builder_end(&builder);
}
const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
@@ -362,7 +348,7 @@ const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
if (strcmp(xml_name, "power-spr.xml") == 0) {
- return pcc->gdb_spr_xml;
+ return pcc->gdb_spr.xml;
}
return NULL;
}
@@ -599,7 +585,8 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
32, "power-vsx.xml", 0);
}
#ifndef CONFIG_USER_ONLY
+ gdb_gen_spr_feature(cs);
gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
- pcc->gdb_num_sprs, "power-spr.xml", 0);
+ pcc->gdb_spr.num_regs, "power-spr.xml", 0);
#endif
}
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 04/23] target/riscv: Use GDBFeature for dynamic XML
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (2 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 03/23] target/ppc: " Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 05/23] gdbstub: Use GDBFeature for gdb_register_coprocessor Alex Bennée
` (18 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-29-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/riscv/cpu.h | 5 +--
target/riscv/cpu.c | 4 +--
target/riscv/gdbstub.c | 81 +++++++++++++++++++-----------------------
3 files changed, 41 insertions(+), 49 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f52dce78baa..5d291a70925 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,6 +24,7 @@
#include "hw/registerfields.h"
#include "hw/qdev-properties.h"
#include "exec/cpu-defs.h"
+#include "exec/gdbstub.h"
#include "qemu/cpu-float.h"
#include "qom/object.h"
#include "qemu/int128.h"
@@ -445,8 +446,8 @@ struct ArchCPU {
CPURISCVState env;
- char *dyn_csr_xml;
- char *dyn_vreg_xml;
+ GDBFeature dyn_csr_feature;
+ GDBFeature dyn_vreg_feature;
/* Configuration Settings */
RISCVCPUConfig cfg;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b8d001d237..1b62e269b90 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2305,9 +2305,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
RISCVCPU *cpu = RISCV_CPU(cs);
if (strcmp(xmlname, "riscv-csr.xml") == 0) {
- return cpu->dyn_csr_xml;
+ return cpu->dyn_csr_feature.xml;
} else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
- return cpu->dyn_vreg_xml;
+ return cpu->dyn_vreg_feature.xml;
}
return NULL;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ca9b71f7bbc..d8da84fa52e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -214,14 +214,15 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
return 0;
}
-static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
+static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- GString *s = g_string_new(NULL);
+ GDBFeatureBuilder builder;
riscv_csr_predicate_fn predicate;
int bitsize = riscv_cpu_max_xlen(mcc);
+ const char *name;
int i;
#if !defined(CONFIG_USER_ONLY)
@@ -233,9 +234,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
bitsize = 64;
}
- g_string_printf(s, "<?xml version=\"1.0\"?>");
- g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
+ gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature,
+ "org.gnu.gdb.riscv.csr", "riscv-csr.xml",
+ base_reg);
for (i = 0; i < CSR_TABLE_SIZE; i++) {
if (env->priv_ver < csr_ops[i].min_priv_ver) {
@@ -243,72 +244,64 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
}
predicate = csr_ops[i].predicate;
if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
- if (csr_ops[i].name) {
- g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
- } else {
- g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
+ g_autofree char *dynamic_name = NULL;
+ name = csr_ops[i].name;
+ if (!name) {
+ dynamic_name = g_strdup_printf("csr%03x", i);
+ name = dynamic_name;
}
- g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
- g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
+
+ gdb_feature_builder_append_reg(&builder, name, bitsize, i,
+ "int", NULL);
}
}
- g_string_append_printf(s, "</feature>");
-
- cpu->dyn_csr_xml = g_string_free(s, false);
+ gdb_feature_builder_end(&builder);
#if !defined(CONFIG_USER_ONLY)
env->debugger = false;
#endif
- return CSR_TABLE_SIZE;
+ return &cpu->dyn_csr_feature;
}
-static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
+static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
{
RISCVCPU *cpu = RISCV_CPU(cs);
- GString *s = g_string_new(NULL);
- g_autoptr(GString) ts = g_string_new("");
- int reg_width = cpu->cfg.vlenb << 3;
- int num_regs = 0;
+ int reg_width = cpu->cfg.vlenb;
+ GDBFeatureBuilder builder;
int i;
- g_string_printf(s, "<?xml version=\"1.0\"?>");
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">");
+ gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature,
+ "org.gnu.gdb.riscv.vector", "riscv-vector.xml",
+ base_reg);
/* First define types and totals in a whole VL */
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
int count = reg_width / vec_lanes[i].size;
- g_string_printf(ts, "%s", vec_lanes[i].id);
- g_string_append_printf(s,
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
- ts->str, vec_lanes[i].gdb_type, count);
+ gdb_feature_builder_append_tag(
+ &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+ vec_lanes[i].id, vec_lanes[i].gdb_type, count);
}
/* Define unions */
- g_string_append_printf(s, "<union id=\"riscv_vector\">");
+ gdb_feature_builder_append_tag(&builder, "<union id=\"riscv_vector\">");
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
- g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>",
- vec_lanes[i].suffix,
- vec_lanes[i].id);
+ gdb_feature_builder_append_tag(&builder,
+ "<field name=\"%c\" type=\"%s\"/>",
+ vec_lanes[i].suffix, vec_lanes[i].id);
}
- g_string_append(s, "</union>");
+ gdb_feature_builder_append_tag(&builder, "</union>");
/* Define vector registers */
for (i = 0; i < 32; i++) {
- g_string_append_printf(s,
- "<reg name=\"v%d\" bitsize=\"%d\""
- " regnum=\"%d\" group=\"vector\""
- " type=\"riscv_vector\"/>",
- i, reg_width, base_reg++);
- num_regs++;
+ gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
+ reg_width, i, "riscv_vector", "vector");
}
- g_string_append_printf(s, "</feature>");
+ gdb_feature_builder_end(&builder);
- cpu->dyn_vreg_xml = g_string_free(s, false);
- return num_regs;
+ return &cpu->dyn_vreg_feature;
}
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
@@ -324,10 +317,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
32, "riscv-32bit-fpu.xml", 0);
}
if (env->misa_ext & RVV) {
- int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_xml(cs, base_reg),
+ ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs,
"riscv-vector.xml", 0);
}
switch (mcc->misa_mxl_max) {
@@ -347,9 +339,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
if (cpu->cfg.ext_zicsr) {
- int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- riscv_gen_dynamic_csr_xml(cs, base_reg),
+ riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs,
"riscv-csr.xml", 0);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 05/23] gdbstub: Use GDBFeature for gdb_register_coprocessor
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (3 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 04/23] target/riscv: " Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 06/23] gdbstub: Use GDBFeature for GDBRegisterState Alex Bennée
` (17 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-30-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/exec/gdbstub.h | 2 +-
gdbstub/gdbstub.c | 13 +++++++------
target/arm/gdbstub.c | 35 +++++++++++++++++++----------------
target/hexagon/cpu.c | 3 +--
target/loongarch/gdbstub.c | 2 +-
target/m68k/helper.c | 6 +++---
target/microblaze/cpu.c | 5 +++--
target/ppc/gdbstub.c | 11 ++++++-----
target/riscv/gdbstub.c | 20 ++++++++++++--------
target/s390x/gdbstub.c | 28 +++++++---------------------
10 files changed, 60 insertions(+), 65 deletions(-)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index d8a3c56fa2b..ac6fce99a64 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -38,7 +38,7 @@ typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
*/
void gdb_register_coprocessor(CPUState *cpu,
gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
- int num_regs, const char *xml, int g_pos);
+ const GDBFeature *feature, int g_pos);
/**
* gdbserver_start: start the gdb server
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 7e73e916bdc..256599c8dfb 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -544,7 +544,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
void gdb_register_coprocessor(CPUState *cpu,
gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
- int num_regs, const char *xml, int g_pos)
+ const GDBFeature *feature, int g_pos)
{
GDBRegisterState *s;
guint i;
@@ -553,7 +553,7 @@ void gdb_register_coprocessor(CPUState *cpu,
for (i = 0; i < cpu->gdb_regs->len; i++) {
/* Check for duplicates. */
s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (strcmp(s->xml, xml) == 0) {
+ if (strcmp(s->xml, feature->xmlname) == 0) {
return;
}
}
@@ -565,17 +565,18 @@ void gdb_register_coprocessor(CPUState *cpu,
g_array_set_size(cpu->gdb_regs, i + 1);
s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
s->base_reg = cpu->gdb_num_regs;
- s->num_regs = num_regs;
+ s->num_regs = feature->num_regs;
s->get_reg = get_reg;
s->set_reg = set_reg;
- s->xml = xml;
+ s->xml = feature->xml;
/* Add to end of list. */
- cpu->gdb_num_regs += num_regs;
+ cpu->gdb_num_regs += feature->num_regs;
if (g_pos) {
if (g_pos != s->base_reg) {
error_report("Error: Bad gdb register numbering for '%s', "
- "expected %d got %d", xml, g_pos, s->base_reg);
+ "expected %d got %d", feature->xml,
+ g_pos, s->base_reg);
} else {
cpu->gdb_num_g_regs = cpu->gdb_num_regs;
}
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 5949adfb31a..f2b201d3125 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -483,14 +483,14 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
*/
#ifdef TARGET_AARCH64
if (isar_feature_aa64_sve(&cpu->isar)) {
- int nreg = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs)->num_regs;
+ GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs);
gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
- aarch64_gdb_set_sve_reg, nreg,
- "sve-registers.xml", 0);
+ aarch64_gdb_set_sve_reg, feature, 0);
} else {
gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
aarch64_gdb_set_fpu_reg,
- 34, "aarch64-fpu.xml", 0);
+ gdb_find_static_feature("aarch64-fpu.xml"),
+ 0);
}
/*
* Note that we report pauth information via the feature name
@@ -501,19 +501,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
if (isar_feature_aa64_pauth(&cpu->isar)) {
gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
aarch64_gdb_set_pauth_reg,
- 4, "aarch64-pauth.xml", 0);
+ gdb_find_static_feature("aarch64-pauth.xml"),
+ 0);
}
#endif
} else {
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
- 49, "arm-neon.xml", 0);
+ gdb_find_static_feature("arm-neon.xml"),
+ 0);
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
- 33, "arm-vfp3.xml", 0);
+ gdb_find_static_feature("arm-vfp3.xml"),
+ 0);
} else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
- 17, "arm-vfp.xml", 0);
+ gdb_find_static_feature("arm-vfp.xml"), 0);
}
if (!arm_feature(env, ARM_FEATURE_M)) {
/*
@@ -521,29 +524,29 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
* expose to gdb.
*/
gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
- 2, "arm-vfp-sysregs.xml", 0);
+ gdb_find_static_feature("arm-vfp-sysregs.xml"),
+ 0);
}
}
if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
- 1, "arm-m-profile-mve.xml", 0);
+ gdb_find_static_feature("arm-m-profile-mve.xml"),
+ 0);
}
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
- arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs)->num_regs,
- "system-registers.xml", 0);
+ arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs),
+ 0);
#ifdef CONFIG_TCG
if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
- arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num_regs,
- "arm-m-system.xml", 0);
+ arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs), 0);
#ifndef CONFIG_USER_ONLY
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
- arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)->num_regs,
- "arm-m-secext.xml", 0);
+ arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs), 0);
}
#endif
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 759ea62814d..ebe804e2931 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -319,8 +319,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,
hexagon_hvx_gdb_write_register,
- NUM_VREGS + NUM_QREGS,
- "hexagon-hvx.xml", 0);
+ gdb_find_static_feature("hexagon-hvx.xml"), 0);
qemu_init_vcpu(cs);
cpu_reset(cs);
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 5fc2f19e965..843a869450e 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -118,5 +118,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
{
gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
- 41, "loongarch-fpu.xml", 0);
+ gdb_find_static_feature("loongarch-fpu.xml"), 0);
}
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 14508dfa118..9808d676a22 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -112,10 +112,10 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_reg,
- 11, "cf-fp.xml", 18);
+ gdb_find_static_feature("cf-fp.xml"), 18);
} else if (m68k_feature(env, M68K_FEATURE_FPU)) {
- gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg,
- m68k_fpu_gdb_set_reg, 11, "m68k-fp.xml", 18);
+ gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_set_reg,
+ gdb_find_static_feature("m68k-fp.xml"), 18);
}
/* TODO: Add [E]MAC registers. */
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 2002231a6b4..2c62cf048c2 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -313,8 +313,9 @@ static void mb_cpu_initfn(Object *obj)
CPUMBState *env = &cpu->env;
gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
- mb_cpu_gdb_write_stack_protect, 2,
- "microblaze-stack-protect.xml", 0);
+ mb_cpu_gdb_write_stack_protect,
+ gdb_find_static_feature("microblaze-stack-protect.xml"),
+ 0);
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index e3be3dbd109..09b852464f3 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -570,23 +570,24 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
{
if (pcc->insns_flags & PPC_FLOAT) {
gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
- 33, "power-fpu.xml", 0);
+ gdb_find_static_feature("power-fpu.xml"), 0);
}
if (pcc->insns_flags & PPC_ALTIVEC) {
gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
- 34, "power-altivec.xml", 0);
+ gdb_find_static_feature("power-altivec.xml"),
+ 0);
}
if (pcc->insns_flags & PPC_SPE) {
gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
- 34, "power-spe.xml", 0);
+ gdb_find_static_feature("power-spe.xml"), 0);
}
if (pcc->insns_flags2 & PPC2_VSX) {
gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
- 32, "power-vsx.xml", 0);
+ gdb_find_static_feature("power-vsx.xml"), 0);
}
#ifndef CONFIG_USER_ONLY
gdb_gen_spr_feature(cs);
gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
- pcc->gdb_spr.num_regs, "power-spr.xml", 0);
+ &pcc->gdb_spr, 0);
#endif
}
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index d8da84fa52e..ec1fc6a29da 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -311,28 +311,32 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
CPURISCVState *env = &cpu->env;
if (env->misa_ext & RVD) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 32, "riscv-64bit-fpu.xml", 0);
+ gdb_find_static_feature("riscv-64bit-fpu.xml"),
+ 0);
} else if (env->misa_ext & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 32, "riscv-32bit-fpu.xml", 0);
+ gdb_find_static_feature("riscv-32bit-fpu.xml"),
+ 0);
}
if (env->misa_ext & RVV) {
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs,
- "riscv-vector.xml", 0);
+ ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
+ 0);
}
switch (mcc->misa_mxl_max) {
case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
- 1, "riscv-32bit-virtual.xml", 0);
+ gdb_find_static_feature("riscv-32bit-virtual.xml"),
+ 0);
break;
case MXL_RV64:
case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
- 1, "riscv-64bit-virtual.xml", 0);
+ gdb_find_static_feature("riscv-64bit-virtual.xml"),
+ 0);
break;
default:
g_assert_not_reached();
@@ -340,7 +344,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
if (cpu->cfg.ext_zicsr) {
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs,
- "riscv-csr.xml", 0);
+ riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs),
+ 0);
}
}
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
index f02fa316e53..256f1c7c6db 100644
--- a/target/s390x/gdbstub.c
+++ b/target/s390x/gdbstub.c
@@ -67,8 +67,6 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
/* the values represent the positions in s390-acr.xml */
#define S390_A0_REGNUM 0
#define S390_A15_REGNUM 15
-/* total number of registers in s390-acr.xml */
-#define S390_NUM_AC_REGS 16
static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n)
{
@@ -96,8 +94,6 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_FPC_REGNUM 0
#define S390_F0_REGNUM 1
#define S390_F15_REGNUM 16
-/* total number of registers in s390-fpr.xml */
-#define S390_NUM_FP_REGS 17
static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n)
{
@@ -130,8 +126,6 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_V15L_REGNUM 15
#define S390_V16_REGNUM 16
#define S390_V31_REGNUM 31
-/* total number of registers in s390-vx.xml */
-#define S390_NUM_VREGS 32
static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n)
{
@@ -170,8 +164,6 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n)
/* the values represent the positions in s390-cr.xml */
#define S390_C0_REGNUM 0
#define S390_C15_REGNUM 15
-/* total number of registers in s390-cr.xml */
-#define S390_NUM_C_REGS 16
#ifndef CONFIG_USER_ONLY
static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n)
@@ -204,8 +196,6 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_VIRT_CPUTM_REGNUM 1
#define S390_VIRT_BEA_REGNUM 2
#define S390_VIRT_PREFIX_REGNUM 3
-/* total number of registers in s390-virt.xml */
-#define S390_NUM_VIRT_REGS 4
static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
{
@@ -252,8 +242,6 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_VIRT_KVM_PFT_REGNUM 1
#define S390_VIRT_KVM_PFS_REGNUM 2
#define S390_VIRT_KVM_PFC_REGNUM 3
-/* total number of registers in s390-virt-kvm.xml */
-#define S390_NUM_VIRT_KVM_REGS 4
static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
{
@@ -301,8 +289,6 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_GS_GSD_REGNUM 1
#define S390_GS_GSSM_REGNUM 2
#define S390_GS_GSEPLA_REGNUM 3
-/* total number of registers in s390-gs.xml */
-#define S390_NUM_GS_REGS 4
static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n)
{
@@ -320,33 +306,33 @@ void s390_cpu_gdb_init(CPUState *cs)
{
gdb_register_coprocessor(cs, cpu_read_ac_reg,
cpu_write_ac_reg,
- S390_NUM_AC_REGS, "s390-acr.xml", 0);
+ gdb_find_static_feature("s390-acr.xml"), 0);
gdb_register_coprocessor(cs, cpu_read_fp_reg,
cpu_write_fp_reg,
- S390_NUM_FP_REGS, "s390-fpr.xml", 0);
+ gdb_find_static_feature("s390-fpr.xml"), 0);
gdb_register_coprocessor(cs, cpu_read_vreg,
cpu_write_vreg,
- S390_NUM_VREGS, "s390-vx.xml", 0);
+ gdb_find_static_feature("s390-vx.xml"), 0);
gdb_register_coprocessor(cs, cpu_read_gs_reg,
cpu_write_gs_reg,
- S390_NUM_GS_REGS, "s390-gs.xml", 0);
+ gdb_find_static_feature("s390-gs.xml"), 0);
#ifndef CONFIG_USER_ONLY
gdb_register_coprocessor(cs, cpu_read_c_reg,
cpu_write_c_reg,
- S390_NUM_C_REGS, "s390-cr.xml", 0);
+ gdb_find_static_feature("s390-cr.xml"), 0);
gdb_register_coprocessor(cs, cpu_read_virt_reg,
cpu_write_virt_reg,
- S390_NUM_VIRT_REGS, "s390-virt.xml", 0);
+ gdb_find_static_feature("s390-virt.xml"), 0);
if (kvm_enabled()) {
gdb_register_coprocessor(cs, cpu_read_virt_kvm_reg,
cpu_write_virt_kvm_reg,
- S390_NUM_VIRT_KVM_REGS, "s390-virt-kvm.xml",
+ gdb_find_static_feature("s390-virt-kvm.xml"),
0);
}
#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 06/23] gdbstub: Use GDBFeature for GDBRegisterState
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (4 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 05/23] gdbstub: Use GDBFeature for gdb_register_coprocessor Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 07/23] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb Alex Bennée
` (16 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240103173349.398526-31-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-5-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
gdbstub/gdbstub.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 256599c8dfb..0ea417b2c9a 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -47,10 +47,9 @@
typedef struct GDBRegisterState {
int base_reg;
- int num_regs;
gdb_get_reg_cb get_reg;
gdb_set_reg_cb set_reg;
- const char *xml;
+ const GDBFeature *feature;
} GDBRegisterState;
GDBState gdbserver_state;
@@ -391,7 +390,7 @@ static const char *get_feature_xml(const char *p, const char **newp,
g_ptr_array_add(
xml,
g_markup_printf_escaped("<xi:include href=\"%s\"/>",
- r->xml));
+ r->feature->xmlname));
}
}
g_ptr_array_add(xml, g_strdup("</target>"));
@@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
if (cpu->gdb_regs) {
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
+ if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
return r->get_reg(env, buf, reg - r->base_reg);
}
}
@@ -534,7 +533,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
if (cpu->gdb_regs) {
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
+ if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
return r->set_reg(env, mem_buf, reg - r->base_reg);
}
}
@@ -553,7 +552,7 @@ void gdb_register_coprocessor(CPUState *cpu,
for (i = 0; i < cpu->gdb_regs->len; i++) {
/* Check for duplicates. */
s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (strcmp(s->xml, feature->xmlname) == 0) {
+ if (s->feature == feature) {
return;
}
}
@@ -565,10 +564,9 @@ void gdb_register_coprocessor(CPUState *cpu,
g_array_set_size(cpu->gdb_regs, i + 1);
s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
s->base_reg = cpu->gdb_num_regs;
- s->num_regs = feature->num_regs;
s->get_reg = get_reg;
s->set_reg = set_reg;
- s->xml = feature->xml;
+ s->feature = feature;
/* Add to end of list. */
cpu->gdb_num_regs += feature->num_regs;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 07/23] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (5 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 06/23] gdbstub: Use GDBFeature for GDBRegisterState Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 08/23] gdbstub: Simplify XML lookup Alex Bennée
` (15 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-32-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/exec/gdbstub.h | 4 +-
target/arm/internals.h | 12 +++---
target/hexagon/internal.h | 4 +-
target/microblaze/cpu.h | 4 +-
gdbstub/gdbstub.c | 6 +--
target/arm/gdbstub.c | 51 ++++++++++++++++--------
target/arm/gdbstub64.c | 27 +++++++++----
target/hexagon/gdbstub.c | 10 ++++-
target/loongarch/gdbstub.c | 11 ++++--
target/m68k/helper.c | 20 ++++++++--
target/microblaze/gdbstub.c | 9 ++++-
target/ppc/gdbstub.c | 46 +++++++++++++++++-----
target/riscv/gdbstub.c | 50 +++++++++++++++++-------
target/s390x/gdbstub.c | 77 ++++++++++++++++++++++++++++---------
14 files changed, 238 insertions(+), 93 deletions(-)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index ac6fce99a64..bcaab1bc750 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -24,8 +24,8 @@ typedef struct GDBFeatureBuilder {
/* Get or set a register. Returns the size of the register. */
-typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg);
-typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
+typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg);
+typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg);
/**
* gdb_register_coprocessor() - register a supplemental set of registers
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 05eb9daac7d..860bcc0c664 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1452,12 +1452,12 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
#ifdef TARGET_AARCH64
GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
-int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
-int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
-int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
-int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
-int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
-int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
+int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
+int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg);
+int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg);
+int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg);
+int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg);
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index d732b6bb3c7..beb08cb7e38 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -33,8 +33,8 @@
int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n);
-int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n);
+int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int n);
+int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n);
void hexagon_debug_vreg(CPUHexagonState *env, int regnum);
void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 446af5dd4ca..c0c7574dbd5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -381,8 +381,8 @@ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);
-int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg);
+int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg);
+int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *buf, int reg);
static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
{
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 0ea417b2c9a..486ceb52d2e 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -502,7 +502,6 @@ const GDBFeature *gdb_find_static_feature(const char *xmlname)
static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUArchState *env = cpu_env(cpu);
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
@@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
- return r->get_reg(env, buf, reg - r->base_reg);
+ return r->get_reg(cpu, buf, reg - r->base_reg);
}
}
}
@@ -523,7 +522,6 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUArchState *env = cpu_env(cpu);
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
@@ -534,7 +532,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
- return r->set_reg(env, mem_buf, reg - r->base_reg);
+ return r->set_reg(cpu, mem_buf, reg - r->base_reg);
}
}
}
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index f2b201d3125..059d84f98e5 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -106,9 +106,10 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return 0;
}
-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
+static int vfp_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg)
{
- ARMCPU *cpu = env_archcpu(env);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
/* VFP data registers are always little-endian. */
@@ -130,9 +131,10 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
return 0;
}
-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
+static int vfp_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg)
{
- ARMCPU *cpu = env_archcpu(env);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
if (reg < nregs) {
@@ -156,8 +158,11 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
-static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
+static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0:
return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
@@ -167,8 +172,11 @@ static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
return 0;
}
-static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
+static int vfp_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0:
env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
@@ -180,8 +188,11 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
-static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
+static int mve_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0:
return gdb_get_reg32(buf, env->v7m.vpr);
@@ -190,8 +201,11 @@ static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
}
}
-static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
+static int mve_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0:
env->v7m.vpr = ldl_p(buf);
@@ -210,9 +224,10 @@ static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
* We return the number of bytes copied
*/
-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
+static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)
{
- ARMCPU *cpu = env_archcpu(env);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
const ARMCPRegInfo *ri;
uint32_t key;
@@ -228,7 +243,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
return 0;
}
-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
+static int arm_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg)
{
return 0;
}
@@ -367,8 +382,11 @@ static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
return gdb_get_reg32(buf, *ptr);
}
-static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
+static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
/*
* Here, we emulate MRS instruction, where CONTROL has a mix of
* banked and non-banked bits.
@@ -379,7 +397,7 @@ static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
return m_sysreg_get(env, buf, reg, env->v7m.secure);
}
-static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
+static int arm_gdb_set_m_systemreg(CPUState *cs, uint8_t *buf, int reg)
{
return 0; /* TODO */
}
@@ -414,12 +432,15 @@ static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs,
* For user-only, we see the non-secure registers via m_systemreg above.
* For secext, encode the non-secure view as even and secure view as odd.
*/
-static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
+static int arm_gdb_get_m_secextreg(CPUState *cs, GByteArray *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
return m_sysreg_get(env, buf, reg >> 1, reg & 1);
}
-static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
+static int arm_gdb_set_m_secextreg(CPUState *cs, uint8_t *buf, int reg)
{
return 0; /* TODO */
}
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 5286d5c6043..caa31ff3fa1 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -72,8 +72,11 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return 0;
}
-int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0 ... 31:
{
@@ -92,8 +95,11 @@ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
}
}
-int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0 ... 31:
/* 128 bit FP register */
@@ -116,9 +122,10 @@ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
}
}
-int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg)
{
- ARMCPU *cpu = env_archcpu(env);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
switch (reg) {
/* The first 32 registers are the zregs */
@@ -164,9 +171,10 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
return 0;
}
-int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
{
- ARMCPU *cpu = env_archcpu(env);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
/* The first 32 registers are the zregs */
switch (reg) {
@@ -210,8 +218,11 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
-int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
switch (reg) {
case 0: /* pauth_dmask */
case 1: /* pauth_cmask */
@@ -241,7 +252,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
}
}
-int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg)
{
/* All pseudo registers are read-only. */
return 0;
diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
index 54d37e006e0..6007e6462b9 100644
--- a/target/hexagon/gdbstub.c
+++ b/target/hexagon/gdbstub.c
@@ -81,8 +81,11 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
return total;
}
-int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n)
+int hexagon_hvx_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
+ HexagonCPU *cpu = HEXAGON_CPU(cs);
+ CPUHexagonState *env = &cpu->env;
+
if (n < NUM_VREGS) {
return gdb_get_vreg(env, mem_buf, n);
}
@@ -115,8 +118,11 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
return MAX_VEC_SIZE_BYTES / 8;
}
-int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n)
+int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ HexagonCPU *cpu = HEXAGON_CPU(cs);
+ CPUHexagonState *env = &cpu->env;
+
if (n < NUM_VREGS) {
return gdb_put_vreg(env, mem_buf, n);
}
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 843a869450e..22c6889011e 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -84,9 +84,11 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return length;
}
-static int loongarch_gdb_get_fpu(CPULoongArchState *env,
- GByteArray *mem_buf, int n)
+static int loongarch_gdb_get_fpu(CPUState *cs, GByteArray *mem_buf, int n)
{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
if (0 <= n && n < 32) {
return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0));
} else if (32 <= n && n < 40) {
@@ -97,9 +99,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,
return 0;
}
-static int loongarch_gdb_set_fpu(CPULoongArchState *env,
- uint8_t *mem_buf, int n)
+static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
int length = 0;
if (0 <= n && n < 32) {
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 9808d676a22..1c33995e5da 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -29,8 +29,11 @@
#define SIGNBIT (1u << 31)
-static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)
+static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (n < 8) {
float_status s;
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
@@ -46,8 +49,11 @@ static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)
return 0;
}
-static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (n < 8) {
float_status s;
env->fregs[n].d = float64_to_floatx80(ldq_p(mem_buf), &s);
@@ -66,8 +72,11 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)
+static int m68k_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (n < 8) {
int len = gdb_get_reg16(mem_buf, env->fregs[n].l.upper);
len += gdb_get_reg16(mem_buf, 0);
@@ -85,8 +94,11 @@ static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)
return 0;
}
-static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (n < 8) {
env->fregs[n].l.upper = lduw_be_p(mem_buf);
env->fregs[n].l.lower = ldq_be_p(mem_buf + 4);
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 29ac6e9c0f7..6ffc5ad0752 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -94,8 +94,10 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_reg32(mem_buf, val);
}
-int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, int n)
+int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
uint32_t val;
switch (n) {
@@ -153,8 +155,11 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return 4;
}
-int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int n)
+int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *mem_buf, int n)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
switch (n) {
case GDB_SP_SHL:
env->slr = ldl_p(mem_buf);
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 09b852464f3..8ca37b6bf95 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -369,8 +369,10 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n)
return -1;
}
-static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
+static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
int reg;
int len;
@@ -385,8 +387,10 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
return len;
}
-static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
int reg;
int len;
@@ -403,8 +407,10 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
}
#endif
-static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
+static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
uint8_t *mem_buf;
if (n < 32) {
gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
@@ -421,8 +427,11 @@ static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
return 0;
}
-static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
ppc_maybe_bswap_register(env, mem_buf, 8);
*cpu_fpr_ptr(env, n) = ldq_p(mem_buf);
@@ -436,8 +445,10 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
+static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
uint8_t *mem_buf;
if (n < 32) {
@@ -462,8 +473,11 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
return 0;
}
-static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
ppc_avr_t *avr = cpu_avr_ptr(env, n);
ppc_maybe_bswap_register(env, mem_buf, 16);
@@ -484,8 +498,11 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
+static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
#if defined(TARGET_PPC64)
gdb_get_reg32(buf, env->gpr[n] >> 32);
@@ -508,8 +525,11 @@ static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
return 0;
}
-static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
#if defined(TARGET_PPC64)
target_ulong lo = (uint32_t)env->gpr[n];
@@ -537,8 +557,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
+static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
@@ -547,8 +570,11 @@ static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
return 0;
}
-static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
ppc_maybe_bswap_register(env, mem_buf, 8);
*cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ec1fc6a29da..546e8692d17 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -108,8 +108,11 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return length;
}
-static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
+static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
if (n < 32) {
if (env->misa_ext & RVD) {
return gdb_get_reg64(buf, env->fpr[n]);
@@ -121,8 +124,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
return 0;
}
-static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
if (n < 32) {
env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
@@ -130,9 +136,11 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
+static int riscv_gdb_get_vector(CPUState *cs, GByteArray *buf, int n)
{
- uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ uint16_t vlenb = cpu->cfg.vlenb;
if (n < 32) {
int i;
int cnt = 0;
@@ -146,9 +154,11 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
return 0;
}
-static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
+static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)
{
- uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ uint16_t vlenb = cpu->cfg.vlenb;
if (n < 32) {
int i;
for (i = 0; i < vlenb; i += 8) {
@@ -160,8 +170,11 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
+static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n)
{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
if (n < CSR_TABLE_SIZE) {
target_ulong val = 0;
int result;
@@ -174,8 +187,11 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
return 0;
}
-static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
if (n < CSR_TABLE_SIZE) {
target_ulong val = ldtul_p(mem_buf);
int result;
@@ -188,25 +204,31 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
+static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)
{
if (n == 0) {
#ifdef CONFIG_USER_ONLY
return gdb_get_regl(buf, 0);
#else
- return gdb_get_regl(buf, cs->priv);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ return gdb_get_regl(buf, env->priv);
#endif
}
return 0;
}
-static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
+static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
{
if (n == 0) {
#ifndef CONFIG_USER_ONLY
- cs->priv = ldtul_p(mem_buf) & 0x3;
- if (cs->priv == PRV_RESERVED) {
- cs->priv = PRV_S;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ env->priv = ldtul_p(mem_buf) & 0x3;
+ if (env->priv == PRV_RESERVED) {
+ env->priv = PRV_S;
}
#endif
return sizeof(target_ulong);
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
index 256f1c7c6db..a9f4eb92adf 100644
--- a/target/s390x/gdbstub.c
+++ b/target/s390x/gdbstub.c
@@ -68,8 +68,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
#define S390_A0_REGNUM 0
#define S390_A15_REGNUM 15
-static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n)
+static int cpu_read_ac_reg(CPUState *cs, GByteArray *buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_A0_REGNUM ... S390_A15_REGNUM:
return gdb_get_reg32(buf, env->aregs[n]);
@@ -78,8 +81,11 @@ static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n)
}
}
-static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_A0_REGNUM ... S390_A15_REGNUM:
env->aregs[n] = ldl_p(mem_buf);
@@ -95,8 +101,11 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_F0_REGNUM 1
#define S390_F15_REGNUM 16
-static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n)
+static int cpu_read_fp_reg(CPUState *cs, GByteArray *buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_FPC_REGNUM:
return gdb_get_reg32(buf, env->fpc);
@@ -107,8 +116,11 @@ static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n)
}
}
-static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_FPC_REGNUM:
env->fpc = ldl_p(mem_buf);
@@ -127,8 +139,10 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_V16_REGNUM 16
#define S390_V31_REGNUM 31
-static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n)
+static int cpu_read_vreg(CPUState *cs, GByteArray *buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
int ret;
switch (n) {
@@ -146,8 +160,11 @@ static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n)
return ret;
}
-static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_vreg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_V0L_REGNUM ... S390_V15L_REGNUM:
env->vregs[n][1] = ldtul_p(mem_buf + 8);
@@ -166,8 +183,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_C15_REGNUM 15
#ifndef CONFIG_USER_ONLY
-static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n)
+static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_C0_REGNUM ... S390_C15_REGNUM:
return gdb_get_regl(buf, env->cregs[n]);
@@ -176,8 +196,11 @@ static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n)
}
}
-static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_c_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_C0_REGNUM ... S390_C15_REGNUM:
env->cregs[n] = ldtul_p(mem_buf);
@@ -197,8 +220,11 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_VIRT_BEA_REGNUM 2
#define S390_VIRT_PREFIX_REGNUM 3
-static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
+static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_VIRT_CKC_REGNUM:
return gdb_get_regl(mem_buf, env->ckc);
@@ -213,24 +239,27 @@ static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
}
}
-static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_virt_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_VIRT_CKC_REGNUM:
env->ckc = ldtul_p(mem_buf);
- cpu_synchronize_post_init(env_cpu(env));
+ cpu_synchronize_post_init(cs);
return 8;
case S390_VIRT_CPUTM_REGNUM:
env->cputm = ldtul_p(mem_buf);
- cpu_synchronize_post_init(env_cpu(env));
+ cpu_synchronize_post_init(cs);
return 8;
case S390_VIRT_BEA_REGNUM:
env->gbea = ldtul_p(mem_buf);
- cpu_synchronize_post_init(env_cpu(env));
+ cpu_synchronize_post_init(cs);
return 8;
case S390_VIRT_PREFIX_REGNUM:
env->psa = ldtul_p(mem_buf);
- cpu_synchronize_post_init(env_cpu(env));
+ cpu_synchronize_post_init(cs);
return 8;
default:
return 0;
@@ -243,8 +272,11 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_VIRT_KVM_PFS_REGNUM 2
#define S390_VIRT_KVM_PFC_REGNUM 3
-static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
+static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_VIRT_KVM_PP_REGNUM:
return gdb_get_regl(mem_buf, env->pp);
@@ -259,8 +291,11 @@ static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
}
}
-static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_virt_kvm_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
switch (n) {
case S390_VIRT_KVM_PP_REGNUM:
env->pp = ldtul_p(mem_buf);
@@ -290,13 +325,19 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
#define S390_GS_GSSM_REGNUM 2
#define S390_GS_GSEPLA_REGNUM 3
-static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n)
+static int cpu_read_gs_reg(CPUState *cs, GByteArray *buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
return gdb_get_regl(buf, env->gscb[n]);
}
-static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
env->gscb[n] = ldtul_p(mem_buf);
cpu_synchronize_post_init(env_cpu(env));
return 8;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 08/23] gdbstub: Simplify XML lookup
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (6 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 07/23] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 09/23] gdbstub: Infer number of core registers from XML Alex Bennée
` (14 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-33-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-7-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/exec/gdbstub.h | 6 +++
gdbstub/gdbstub.c | 118 +++++++++++++++++++++--------------------
hw/core/cpu-common.c | 5 +-
3 files changed, 69 insertions(+), 60 deletions(-)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index bcaab1bc750..82a8afa237f 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -27,6 +27,12 @@ typedef struct GDBFeatureBuilder {
typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg);
typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg);
+/**
+ * gdb_init_cpu(): Initialize the CPU for gdbstub.
+ * @cpu: The CPU to be initialized.
+ */
+void gdb_init_cpu(CPUState *cpu);
+
/**
* gdb_register_coprocessor() - register a supplemental set of registers
* @cpu - the CPU associated with registers
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 486ceb52d2e..d573f808d2e 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -352,6 +352,7 @@ static const char *get_feature_xml(const char *p, const char **newp,
{
CPUState *cpu = gdb_get_first_cpu_in_process(process);
CPUClass *cc = CPU_GET_CLASS(cpu);
+ GDBRegisterState *r;
size_t len;
/*
@@ -365,7 +366,6 @@ static const char *get_feature_xml(const char *p, const char **newp,
/* Is it the main target xml? */
if (strncmp(p, "target.xml", len) == 0) {
if (!process->target_xml) {
- GDBRegisterState *r;
g_autoptr(GPtrArray) xml = g_ptr_array_new_with_free_func(g_free);
g_ptr_array_add(
@@ -380,18 +380,12 @@ static const char *get_feature_xml(const char *p, const char **newp,
g_markup_printf_escaped("<architecture>%s</architecture>",
cc->gdb_arch_name(cpu)));
}
- g_ptr_array_add(
- xml,
- g_markup_printf_escaped("<xi:include href=\"%s\"/>",
- cc->gdb_core_xml_file));
- if (cpu->gdb_regs) {
- for (guint i = 0; i < cpu->gdb_regs->len; i++) {
- r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- g_ptr_array_add(
- xml,
- g_markup_printf_escaped("<xi:include href=\"%s\"/>",
- r->feature->xmlname));
- }
+ for (guint i = 0; i < cpu->gdb_regs->len; i++) {
+ r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ g_ptr_array_add(
+ xml,
+ g_markup_printf_escaped("<xi:include href=\"%s\"/>",
+ r->feature->xmlname));
}
g_ptr_array_add(xml, g_strdup("</target>"));
g_ptr_array_add(xml, NULL);
@@ -400,20 +394,11 @@ static const char *get_feature_xml(const char *p, const char **newp,
}
return process->target_xml;
}
- /* Is it dynamically generated by the target? */
- if (cc->gdb_get_dynamic_xml) {
- g_autofree char *xmlname = g_strndup(p, len);
- const char *xml = cc->gdb_get_dynamic_xml(cpu, xmlname);
- if (xml) {
- return xml;
- }
- }
- /* Is it one of the encoded gdb-xml/ files? */
- for (int i = 0; gdb_static_features[i].xmlname; i++) {
- const char *name = gdb_static_features[i].xmlname;
- if ((strncmp(name, p, len) == 0) &&
- strlen(name) == len) {
- return gdb_static_features[i].xml;
+ /* Is it one of the features? */
+ for (guint i = 0; i < cpu->gdb_regs->len; i++) {
+ r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ if (strncmp(p, r->feature->xmlname, len) == 0) {
+ return r->feature->xml;
}
}
@@ -508,12 +493,10 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
return cc->gdb_read_register(cpu, buf, reg);
}
- if (cpu->gdb_regs) {
- for (guint i = 0; i < cpu->gdb_regs->len; i++) {
- r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
- return r->get_reg(cpu, buf, reg - r->base_reg);
- }
+ for (guint i = 0; i < cpu->gdb_regs->len; i++) {
+ r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
+ return r->get_reg(cpu, buf, reg - r->base_reg);
}
}
return 0;
@@ -528,51 +511,70 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
return cc->gdb_write_register(cpu, mem_buf, reg);
}
- if (cpu->gdb_regs) {
- for (guint i = 0; i < cpu->gdb_regs->len; i++) {
- r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
- return r->set_reg(cpu, mem_buf, reg - r->base_reg);
- }
+ for (guint i = 0; i < cpu->gdb_regs->len; i++) {
+ r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
+ return r->set_reg(cpu, mem_buf, reg - r->base_reg);
}
}
return 0;
}
+static void gdb_register_feature(CPUState *cpu, int base_reg,
+ gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
+ const GDBFeature *feature)
+{
+ GDBRegisterState s = {
+ .base_reg = base_reg,
+ .get_reg = get_reg,
+ .set_reg = set_reg,
+ .feature = feature
+ };
+
+ g_array_append_val(cpu->gdb_regs, s);
+}
+
+void gdb_init_cpu(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ const GDBFeature *feature;
+
+ cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState));
+
+ if (cc->gdb_core_xml_file) {
+ feature = gdb_find_static_feature(cc->gdb_core_xml_file);
+ gdb_register_feature(cpu, 0,
+ cc->gdb_read_register, cc->gdb_write_register,
+ feature);
+ }
+
+ cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
+}
+
void gdb_register_coprocessor(CPUState *cpu,
gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
const GDBFeature *feature, int g_pos)
{
GDBRegisterState *s;
guint i;
+ int base_reg = cpu->gdb_num_regs;
- if (cpu->gdb_regs) {
- for (i = 0; i < cpu->gdb_regs->len; i++) {
- /* Check for duplicates. */
- s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- if (s->feature == feature) {
- return;
- }
+ for (i = 0; i < cpu->gdb_regs->len; i++) {
+ /* Check for duplicates. */
+ s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ if (s->feature == feature) {
+ return;
}
- } else {
- cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState));
- i = 0;
}
- g_array_set_size(cpu->gdb_regs, i + 1);
- s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
- s->base_reg = cpu->gdb_num_regs;
- s->get_reg = get_reg;
- s->set_reg = set_reg;
- s->feature = feature;
+ gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature);
/* Add to end of list. */
cpu->gdb_num_regs += feature->num_regs;
if (g_pos) {
- if (g_pos != s->base_reg) {
+ if (g_pos != base_reg) {
error_report("Error: Bad gdb register numbering for '%s', "
- "expected %d got %d", feature->xml,
- g_pos, s->base_reg);
+ "expected %d got %d", feature->xml, g_pos, base_reg);
} else {
cpu->gdb_num_g_regs = cpu->gdb_num_regs;
}
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 67db07741d7..fe16d0d9df8 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -27,6 +27,7 @@
#include "qemu/main-loop.h"
#include "exec/log.h"
#include "exec/cpu-common.h"
+#include "exec/gdbstub.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "sysemu/tcg.h"
@@ -240,11 +241,10 @@ static void cpu_common_unrealizefn(DeviceState *dev)
static void cpu_common_initfn(Object *obj)
{
CPUState *cpu = CPU(obj);
- CPUClass *cc = CPU_GET_CLASS(obj);
+ gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
- cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
/* user-mode doesn't have configurable SMP topology */
/* the default value is changed by qemu_init_vcpu() for system-mode */
cpu->nr_cores = 1;
@@ -264,6 +264,7 @@ static void cpu_common_finalize(Object *obj)
{
CPUState *cpu = CPU(obj);
+ g_array_free(cpu->gdb_regs, TRUE);
qemu_lockcnt_destroy(&cpu->in_ioctl_lock);
qemu_mutex_destroy(&cpu->work_mutex);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 09/23] gdbstub: Infer number of core registers from XML
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (7 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 08/23] gdbstub: Simplify XML lookup Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 10/23] hw/core/cpu: Remove gdb_get_dynamic_xml member Alex Bennée
` (13 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-34-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 3 ++-
target/s390x/cpu.h | 2 --
gdbstub/gdbstub.c | 5 ++++-
target/arm/cpu.c | 1 -
target/arm/cpu64.c | 1 -
target/avr/cpu.c | 1 -
target/hexagon/cpu.c | 1 -
target/i386/cpu.c | 2 --
target/loongarch/cpu.c | 2 --
target/m68k/cpu.c | 1 -
target/microblaze/cpu.c | 1 -
target/riscv/cpu.c | 1 -
target/rx/cpu.c | 1 -
target/s390x/cpu.c | 1 -
14 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4385ce54c99..1bbf21b2201 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -126,7 +126,8 @@ struct SysemuCPUOps;
* @gdb_adjust_breakpoint: Callback for adjusting the address of a
* breakpoint. Used by AVR to handle a gdb mis-feature with
* its Harvard architecture split code and data.
- * @gdb_num_core_regs: Number of core registers accessible to GDB.
+ * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer
+ * from @gdb_core_xml_file.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
* before the insn which triggers a watchpoint rather than after it.
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index d37a49b4d92..43a46a5a068 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -491,8 +491,6 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
#define S390_R13_REGNUM 15
#define S390_R14_REGNUM 16
#define S390_R15_REGNUM 17
-/* Total Core Registers. */
-#define S390_NUM_CORE_REGS 18
static inline void setcc(S390CPU *cpu, uint64_t cc)
{
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index d573f808d2e..f766ee277a0 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -546,9 +546,12 @@ void gdb_init_cpu(CPUState *cpu)
gdb_register_feature(cpu, 0,
cc->gdb_read_register, cc->gdb_write_register,
feature);
+ cpu->gdb_num_regs = cpu->gdb_num_g_regs = feature->num_regs;
}
- cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
+ if (cc->gdb_num_core_regs) {
+ cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
+ }
}
void gdb_register_coprocessor(CPUState *cpu,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5fa86bc8d55..84887084d95 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2515,7 +2515,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &arm_sysemu_ops;
#endif
- cc->gdb_num_core_regs = 26;
cc->gdb_arch_name = arm_gdb_arch_name;
cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8e30a7993ea..869d8dd24ee 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -793,7 +793,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
- cc->gdb_num_core_regs = 34;
cc->gdb_core_xml_file = "aarch64-core.xml";
cc->gdb_arch_name = aarch64_gdb_arch_name;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a40f445af21..a50170bc69a 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -251,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
- cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "avr-cpu.xml";
cc->tcg_ops = &avr_tcg_ops;
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index ebe804e2931..a10d87b8220 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -362,7 +362,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
cc->get_pc = hexagon_cpu_get_pc;
cc->gdb_read_register = hexagon_gdb_read_register;
cc->gdb_write_register = hexagon_gdb_write_register;
- cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS;
cc->gdb_stop_before_watchpoint = true;
cc->gdb_core_xml_file = "hexagon-core.xml";
cc->disas_set_info = hexagon_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0cd32a6fce3..71c14a6d3c8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7979,10 +7979,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_arch_name = x86_gdb_arch_name;
#ifdef TARGET_X86_64
cc->gdb_core_xml_file = "i386-64bit.xml";
- cc->gdb_num_core_regs = 66;
#else
cc->gdb_core_xml_file = "i386-32bit.xml";
- cc->gdb_num_core_regs = 50;
#endif
cc->disas_set_info = x86_disas_set_info;
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 7dc50bf35fc..bc2684179f2 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -815,7 +815,6 @@ static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
{
CPUClass *cc = CPU_CLASS(c);
- cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "loongarch-base32.xml";
cc->gdb_arch_name = loongarch32_gdb_arch_name;
}
@@ -829,7 +828,6 @@ static void loongarch64_cpu_class_init(ObjectClass *c, void *data)
{
CPUClass *cc = CPU_CLASS(c);
- cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "loongarch-base64.xml";
cc->gdb_arch_name = loongarch64_gdb_arch_name;
}
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 8a8392e6945..e228a0b18b2 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -568,7 +568,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
- cc->gdb_num_core_regs = 18;
cc->tcg_ops = &m68k_tcg_ops;
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 2c62cf048c2..e533e7a95ec 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -444,7 +444,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
- cc->gdb_num_core_regs = 32 + 25;
cc->gdb_core_xml_file = "microblaze-core.xml";
cc->disas_set_info = mb_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b62e269b90..dd8a0e94897 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2352,7 +2352,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
cc->get_pc = riscv_cpu_get_pc;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
- cc->gdb_num_core_regs = 33;
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 5205167da17..2f878d08d6d 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -221,7 +221,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->disas_set_info = rx_cpu_disas_set_info;
- cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "rx-core.xml";
cc->tcg_ops = &rx_tcg_ops;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 49a2341accf..f7194534aeb 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -368,7 +368,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
s390_cpu_class_init_sysemu(cc);
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
- cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
cc->gdb_core_xml_file = "s390x-core64.xml";
cc->gdb_arch_name = s390_gdb_arch_name;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 10/23] hw/core/cpu: Remove gdb_get_dynamic_xml member
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (8 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 09/23] gdbstub: Infer number of core registers from XML Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 11/23] gdbstub: Add members to identify registers to GDBFeature Alex Bennée
` (12 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
This function is no longer used.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-35-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 4 ----
target/arm/cpu.h | 6 ------
target/ppc/cpu.h | 1 -
target/arm/cpu.c | 1 -
target/arm/gdbstub.c | 18 ------------------
target/ppc/cpu_init.c | 3 ---
target/ppc/gdbstub.c | 10 ----------
target/riscv/cpu.c | 14 --------------
8 files changed, 57 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1bbf21b2201..4b659799b00 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -133,9 +133,6 @@ struct SysemuCPUOps;
* before the insn which triggers a watchpoint rather than after it.
* @gdb_arch_name: Optional callback that returns the architecture name known
* to GDB. The caller must free the returned string with g_free.
- * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
- * gdb stub. Returns a pointer to the XML contents for the specified XML file
- * or NULL if the CPU doesn't have a dynamically generated content for it.
* @disas_set_info: Setup architecture specific components of disassembly info
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
@@ -167,7 +164,6 @@ struct CPUClass {
const char *gdb_core_xml_file;
const gchar * (*gdb_arch_name)(CPUState *cpu);
- const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 508a9c1e0d6..a5b3d8f7da7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1159,12 +1159,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-/* Returns the dynamically generated XML for the gdb stub.
- * Returns a pointer to the XML contents for the specified XML file or NULL
- * if the XML name doesn't match the predefined one.
- */
-const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
-
int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 200652e2c87..a15e7c38faf 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1524,7 +1524,6 @@ int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
#ifndef CONFIG_USER_ONLY
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
#endif
int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 84887084d95..b2ea5d65132 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2516,7 +2516,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_arch_name = arm_gdb_arch_name;
- cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 059d84f98e5..a3bb73cfa7c 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -474,24 +474,6 @@ static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs,
#endif
#endif /* CONFIG_TCG */
-const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
-{
- ARMCPU *cpu = ARM_CPU(cs);
-
- if (strcmp(xmlname, "system-registers.xml") == 0) {
- return cpu->dyn_sysreg_feature.desc.xml;
- } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
- return cpu->dyn_svereg_feature.desc.xml;
- } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
- return cpu->dyn_m_systemreg_feature.desc.xml;
-#ifndef CONFIG_USER_ONLY
- } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
- return cpu->dyn_m_secextreg_feature.desc.xml;
-#endif
- }
- return NULL;
-}
-
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
{
CPUState *cs = CPU(cpu);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 4f6903d3f16..9aae02115bf 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7385,9 +7385,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 71;
-#ifndef CONFIG_USER_ONLY
- cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
-#endif
#ifdef USE_APPLE_GDB
cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 8ca37b6bf95..f47878a67bd 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -342,16 +342,6 @@ static void gdb_gen_spr_feature(CPUState *cs)
gdb_feature_builder_end(&builder);
}
-
-const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
-
- if (strcmp(xml_name, "power-spr.xml") == 0) {
- return pcc->gdb_spr.xml;
- }
- return NULL;
-}
#endif
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dd8a0e94897..5ff0192c527 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2300,19 +2300,6 @@ static const gchar *riscv_gdb_arch_name(CPUState *cs)
}
}
-static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
-
- if (strcmp(xmlname, "riscv-csr.xml") == 0) {
- return cpu->dyn_csr_feature.xml;
- } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
- return cpu->dyn_vreg_feature.xml;
- }
-
- return NULL;
-}
-
#ifndef CONFIG_USER_ONLY
static int64_t riscv_get_arch_id(CPUState *cs)
{
@@ -2359,7 +2346,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
cc->get_arch_id = riscv_get_arch_id;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
- cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 11/23] gdbstub: Add members to identify registers to GDBFeature
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (9 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 10/23] hw/core/cpu: Remove gdb_get_dynamic_xml member Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 12/23] plugins: remove previous n_vcpus functions from API Alex Bennée
` (11 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-36-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/exec/gdbstub.h | 3 +++
gdbstub/gdbstub.c | 12 +++++++++---
target/riscv/gdbstub.c | 4 +---
scripts/feature_to_c.py | 14 +++++++++++++-
4 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 82a8afa237f..da9ddfe54c5 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -13,12 +13,15 @@
typedef struct GDBFeature {
const char *xmlname;
const char *xml;
+ const char *name;
+ const char * const *regs;
int num_regs;
} GDBFeature;
typedef struct GDBFeatureBuilder {
GDBFeature *feature;
GPtrArray *xml;
+ GPtrArray *regs;
int base_reg;
} GDBFeatureBuilder;
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index f766ee277a0..a55b5e6581a 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -419,9 +419,10 @@ void gdb_feature_builder_init(GDBFeatureBuilder *builder, GDBFeature *feature,
builder->feature = feature;
builder->xml = g_ptr_array_new();
g_ptr_array_add(builder->xml, header);
+ builder->regs = g_ptr_array_new();
builder->base_reg = base_reg;
feature->xmlname = xmlname;
- feature->num_regs = 0;
+ feature->name = name;
}
void gdb_feature_builder_append_tag(const GDBFeatureBuilder *builder,
@@ -440,10 +441,12 @@ void gdb_feature_builder_append_reg(const GDBFeatureBuilder *builder,
const char *type,
const char *group)
{
- if (builder->feature->num_regs < regnum) {
- builder->feature->num_regs = regnum;
+ if (builder->regs->len <= regnum) {
+ g_ptr_array_set_size(builder->regs, regnum + 1);
}
+ builder->regs->pdata[regnum] = (gpointer *)name;
+
if (group) {
gdb_feature_builder_append_tag(
builder,
@@ -469,6 +472,9 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *builder)
}
g_ptr_array_free(builder->xml, TRUE);
+
+ builder->feature->num_regs = builder->regs->len;
+ builder->feature->regs = (void *)g_ptr_array_free(builder->regs, FALSE);
}
const GDBFeature *gdb_find_static_feature(const char *xmlname)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 546e8692d17..be7a02cd903 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -266,11 +266,9 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
}
predicate = csr_ops[i].predicate;
if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
- g_autofree char *dynamic_name = NULL;
name = csr_ops[i].name;
if (!name) {
- dynamic_name = g_strdup_printf("csr%03x", i);
- name = dynamic_name;
+ name = g_strdup_printf("csr%03x", i);
}
gdb_feature_builder_append_reg(&builder, name, bitsize, i,
diff --git a/scripts/feature_to_c.py b/scripts/feature_to_c.py
index e04d6b2df7f..807af0e685c 100644
--- a/scripts/feature_to_c.py
+++ b/scripts/feature_to_c.py
@@ -50,7 +50,9 @@ def writeliteral(indent, bytes):
sys.stderr.write(f'unexpected start tag: {element.tag}\n')
exit(1)
+ feature_name = element.attrib['name']
regnum = 0
+ regnames = []
regnums = []
tags = ['feature']
for event, element in events:
@@ -67,6 +69,7 @@ def writeliteral(indent, bytes):
if 'regnum' in element.attrib:
regnum = int(element.attrib['regnum'])
+ regnames.append(element.attrib['name'])
regnums.append(regnum)
regnum += 1
@@ -85,6 +88,15 @@ def writeliteral(indent, bytes):
writeliteral(8, bytes(os.path.basename(input), 'utf-8'))
sys.stdout.write(',\n')
writeliteral(8, read)
- sys.stdout.write(f',\n {num_regs},\n }},\n')
+ sys.stdout.write(',\n')
+ writeliteral(8, bytes(feature_name, 'utf-8'))
+ sys.stdout.write(',\n (const char * const []) {\n')
+
+ for index, regname in enumerate(regnames):
+ sys.stdout.write(f' [{regnums[index] - base_reg}] =\n')
+ writeliteral(16, bytes(regname, 'utf-8'))
+ sys.stdout.write(',\n')
+
+ sys.stdout.write(f' }},\n {num_regs},\n }},\n')
sys.stdout.write(' { NULL }\n};\n')
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 12/23] plugins: remove previous n_vcpus functions from API
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (10 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 11/23] gdbstub: Add members to identify registers to GDBFeature Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 13/23] plugins: add qemu_plugin_num_vcpus function Alex Bennée
` (10 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
This information is already accessible using qemu_info_t during plugin
install.
We will introduce another function (qemu_plugin_num_vcpus) which
represent how many cpus were enabled, by tracking new cpu indexes.
It's a breaking change, so we bump API version.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213094009.150349-2-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/qemu/qemu-plugin.h | 10 +++-------
plugins/plugin.h | 2 +-
contrib/plugins/cache.c | 2 +-
plugins/api.c | 30 ------------------------------
plugins/qemu-plugins.symbols | 2 --
5 files changed, 5 insertions(+), 41 deletions(-)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 4daab6efd29..e45181c793c 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugin.h
@@ -50,11 +50,13 @@ typedef uint64_t qemu_plugin_id_t;
*
* The plugins export the API they were built against by exposing the
* symbol qemu_plugin_version which can be checked.
+ *
+ * version 2: removed qemu_plugin_n_vcpus and qemu_plugin_n_max_vcpus
*/
extern QEMU_PLUGIN_EXPORT int qemu_plugin_version;
-#define QEMU_PLUGIN_VERSION 1
+#define QEMU_PLUGIN_VERSION 2
/**
* struct qemu_info_t - system information for plugins
@@ -643,12 +645,6 @@ QEMU_PLUGIN_API
void qemu_plugin_register_atexit_cb(qemu_plugin_id_t id,
qemu_plugin_udata_cb_t cb, void *userdata);
-/* returns -1 in user-mode */
-int qemu_plugin_n_vcpus(void);
-
-/* returns -1 in user-mode */
-int qemu_plugin_n_max_vcpus(void);
-
/**
* qemu_plugin_outs() - output string via QEMU's logging system
* @string: a string
diff --git a/plugins/plugin.h b/plugins/plugin.h
index 5eb2fdbc85e..90f3f324ab6 100644
--- a/plugins/plugin.h
+++ b/plugins/plugin.h
@@ -15,7 +15,7 @@
#include <gmodule.h>
#include "qemu/qht.h"
-#define QEMU_PLUGIN_MIN_VERSION 0
+#define QEMU_PLUGIN_MIN_VERSION 2
/* global state */
struct qemu_plugin_state {
diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c
index 9e7ade3b374..c5c8ac75a9c 100644
--- a/contrib/plugins/cache.c
+++ b/contrib/plugins/cache.c
@@ -767,7 +767,7 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
policy = LRU;
- cores = sys ? qemu_plugin_n_vcpus() : 1;
+ cores = sys ? info->system.smp_vcpus : 1;
for (i = 0; i < argc; i++) {
char *opt = argv[i];
diff --git a/plugins/api.c b/plugins/api.c
index 5521b0ad36c..2926b1961a8 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -342,36 +342,6 @@ const char *qemu_plugin_hwaddr_device_name(const struct qemu_plugin_hwaddr *h)
#endif
}
-/*
- * Queries to the number and potential maximum number of vCPUs there
- * will be. This helps the plugin dimension per-vcpu arrays.
- */
-
-#ifndef CONFIG_USER_ONLY
-static MachineState * get_ms(void)
-{
- return MACHINE(qdev_get_machine());
-}
-#endif
-
-int qemu_plugin_n_vcpus(void)
-{
-#ifdef CONFIG_USER_ONLY
- return -1;
-#else
- return get_ms()->smp.cpus;
-#endif
-}
-
-int qemu_plugin_n_max_vcpus(void)
-{
-#ifdef CONFIG_USER_ONLY
- return -1;
-#else
- return get_ms()->smp.max_cpus;
-#endif
-}
-
/*
* Plugin output
*/
diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
index 71f6c90549d..ca806000d54 100644
--- a/plugins/qemu-plugins.symbols
+++ b/plugins/qemu-plugins.symbols
@@ -16,8 +16,6 @@
qemu_plugin_mem_is_sign_extended;
qemu_plugin_mem_is_store;
qemu_plugin_mem_size_shift;
- qemu_plugin_n_max_vcpus;
- qemu_plugin_n_vcpus;
qemu_plugin_outs;
qemu_plugin_path_to_binary;
qemu_plugin_register_atexit_cb;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 13/23] plugins: add qemu_plugin_num_vcpus function
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (11 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 12/23] plugins: remove previous n_vcpus functions from API Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 14/23] plugins: fix order of init/idle/resume callback Alex Bennée
` (9 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
We now keep track of how many vcpus were started. This way, a plugin can
easily query number of any vcpus at any point of execution, which
unifies user and system mode workflows.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213094009.150349-3-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/qemu/qemu-plugin.h | 3 +++
plugins/plugin.h | 4 ++++
plugins/api.c | 5 +++++
plugins/core.c | 6 ++++++
plugins/qemu-plugins.symbols | 1 +
5 files changed, 19 insertions(+)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index e45181c793c..93981f8f89f 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugin.h
@@ -645,6 +645,9 @@ QEMU_PLUGIN_API
void qemu_plugin_register_atexit_cb(qemu_plugin_id_t id,
qemu_plugin_udata_cb_t cb, void *userdata);
+/* returns how many vcpus were started at this point */
+int qemu_plugin_num_vcpus(void);
+
/**
* qemu_plugin_outs() - output string via QEMU's logging system
* @string: a string
diff --git a/plugins/plugin.h b/plugins/plugin.h
index 90f3f324ab6..00b3509f708 100644
--- a/plugins/plugin.h
+++ b/plugins/plugin.h
@@ -44,6 +44,8 @@ struct qemu_plugin_state {
* the code cache is flushed.
*/
struct qht dyn_cb_arr_ht;
+ /* How many vcpus were started */
+ int num_vcpus;
};
@@ -97,4 +99,6 @@ void plugin_register_vcpu_mem_cb(GArray **arr,
void exec_inline_op(struct qemu_plugin_dyn_cb *cb);
+int plugin_num_vcpus(void);
+
#endif /* PLUGIN_H */
diff --git a/plugins/api.c b/plugins/api.c
index 2926b1961a8..116b8bd603c 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -342,6 +342,11 @@ const char *qemu_plugin_hwaddr_device_name(const struct qemu_plugin_hwaddr *h)
#endif
}
+int qemu_plugin_num_vcpus(void)
+{
+ return plugin_num_vcpus();
+}
+
/*
* Plugin output
*/
diff --git a/plugins/core.c b/plugins/core.c
index ee2fa41af9e..caa66311351 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -213,6 +213,7 @@ void qemu_plugin_vcpu_init_hook(CPUState *cpu)
bool success;
qemu_rec_mutex_lock(&plugin.lock);
+ plugin.num_vcpus = MAX(plugin.num_vcpus, cpu->cpu_index + 1);
plugin_cpu_update__locked(&cpu->cpu_index, NULL, NULL);
success = g_hash_table_insert(plugin.cpu_ht, &cpu->cpu_index,
&cpu->cpu_index);
@@ -570,3 +571,8 @@ static void __attribute__((__constructor__)) plugin_init(void)
QHT_MODE_AUTO_RESIZE);
atexit(qemu_plugin_atexit_cb);
}
+
+int plugin_num_vcpus(void)
+{
+ return plugin.num_vcpus;
+}
diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
index ca806000d54..adb67608598 100644
--- a/plugins/qemu-plugins.symbols
+++ b/plugins/qemu-plugins.symbols
@@ -16,6 +16,7 @@
qemu_plugin_mem_is_sign_extended;
qemu_plugin_mem_is_store;
qemu_plugin_mem_size_shift;
+ qemu_plugin_num_vcpus;
qemu_plugin_outs;
qemu_plugin_path_to_binary;
qemu_plugin_register_atexit_cb;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 14/23] plugins: fix order of init/idle/resume callback
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (12 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 13/23] plugins: add qemu_plugin_num_vcpus function Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 15/23] cpu: call plugin init hook asynchronously Alex Bennée
` (8 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
We found that vcpu_init_hook was called *after* idle callback.
vcpu_init is called from cpu_realize_fn, while idle/resume cb are called
from qemu_wait_io_event (in vcpu thread).
This change ensures we only call idle and resume cb only once a plugin
was init for a given vcpu.
Next change in the series will run vcpu_init asynchronously, which will
make it run *after* resume callback as well. So we fix this now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20240213094009.150349-4-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
plugins/core.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/plugins/core.c b/plugins/core.c
index caa66311351..2392bbb8889 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -391,12 +391,17 @@ void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret)
void qemu_plugin_vcpu_idle_cb(CPUState *cpu)
{
- plugin_vcpu_cb__simple(cpu, QEMU_PLUGIN_EV_VCPU_IDLE);
+ /* idle and resume cb may be called before init, ignore in this case */
+ if (cpu->cpu_index < plugin.num_vcpus) {
+ plugin_vcpu_cb__simple(cpu, QEMU_PLUGIN_EV_VCPU_IDLE);
+ }
}
void qemu_plugin_vcpu_resume_cb(CPUState *cpu)
{
- plugin_vcpu_cb__simple(cpu, QEMU_PLUGIN_EV_VCPU_RESUME);
+ if (cpu->cpu_index < plugin.num_vcpus) {
+ plugin_vcpu_cb__simple(cpu, QEMU_PLUGIN_EV_VCPU_RESUME);
+ }
}
void qemu_plugin_register_vcpu_idle_cb(qemu_plugin_id_t id,
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 15/23] cpu: call plugin init hook asynchronously
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (13 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 14/23] plugins: fix order of init/idle/resume callback Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 16/23] plugins: Use different helpers when reading registers Alex Bennée
` (7 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
This ensures we run during a cpu_exec, which allows to call start/end
exclusive from this init hook (needed for new scoreboard API introduced
later).
async work is run before any tb is translated/executed, so we can
guarantee plugin init will be called before any other hook.
The previous change made sure that any idle/resume cb call will not be
done before initializing plugin for a given vcpu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20240213094009.150349-5-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/core/cpu-common.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index fe16d0d9df8..68786360ea5 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -194,6 +194,11 @@ static void cpu_common_parse_features(const char *typename, char *features,
}
}
+static void qemu_plugin_vcpu_init__async(CPUState *cpu, run_on_cpu_data unused)
+{
+ qemu_plugin_vcpu_init_hook(cpu);
+}
+
static void cpu_common_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cpu = CPU(dev);
@@ -217,9 +222,9 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
cpu_resume(cpu);
}
- /* Plugin initialization must wait until the cpu is fully realized. */
+ /* Plugin initialization must wait until the cpu start executing code */
if (tcg_enabled()) {
- qemu_plugin_vcpu_init_hook(cpu);
+ async_run_on_cpu(cpu, qemu_plugin_vcpu_init__async, RUN_ON_CPU_NULL);
}
/* NOTE: latest generic point where the cpu is fully realized */
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 16/23] plugins: Use different helpers when reading registers
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (14 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 15/23] cpu: call plugin init hook asynchronously Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 17/23] gdbstub: expose api to find registers Alex Bennée
` (6 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
From: Akihiko Odaki <akihiko.odaki@daynix.com>
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20240103173349.398526-37-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-12-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/plugin-helpers.h | 3 ++-
include/qemu/plugin.h | 1 +
accel/tcg/plugin-gen.c | 43 ++++++++++++++++++++++++++++++++++----
plugins/api.c | 12 +++++++++--
4 files changed, 52 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h
index 8e685e06545..11796436f35 100644
--- a/accel/tcg/plugin-helpers.h
+++ b/accel/tcg/plugin-helpers.h
@@ -1,4 +1,5 @@
#ifdef CONFIG_PLUGIN
-DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, void, i32, ptr)
+DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb_no_wg, TCG_CALL_NO_WG | TCG_CALL_PLUGIN, void, i32, ptr)
+DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb_no_rwg, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, void, i32, ptr)
DEF_HELPER_FLAGS_4(plugin_vcpu_mem_cb, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, void, i32, i32, i64, ptr)
#endif
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
index 7fdc3a4849f..b0c5ac68293 100644
--- a/include/qemu/plugin.h
+++ b/include/qemu/plugin.h
@@ -73,6 +73,7 @@ enum plugin_dyn_cb_type {
enum plugin_dyn_cb_subtype {
PLUGIN_CB_REGULAR,
+ PLUGIN_CB_REGULAR_R,
PLUGIN_CB_INLINE,
PLUGIN_N_CB_SUBTYPES,
};
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 78b331b2510..b37ce7683e6 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -79,6 +79,7 @@ enum plugin_gen_from {
enum plugin_gen_cb {
PLUGIN_GEN_CB_UDATA,
+ PLUGIN_GEN_CB_UDATA_R,
PLUGIN_GEN_CB_INLINE,
PLUGIN_GEN_CB_MEM,
PLUGIN_GEN_ENABLE_MEM_HELPER,
@@ -90,7 +91,10 @@ enum plugin_gen_cb {
* These helpers are stubs that get dynamically switched out for calls
* direct to the plugin if they are subscribed to.
*/
-void HELPER(plugin_vcpu_udata_cb)(uint32_t cpu_index, void *udata)
+void HELPER(plugin_vcpu_udata_cb_no_wg)(uint32_t cpu_index, void *udata)
+{ }
+
+void HELPER(plugin_vcpu_udata_cb_no_rwg)(uint32_t cpu_index, void *udata)
{ }
void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index,
@@ -98,7 +102,7 @@ void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index,
void *userdata)
{ }
-static void gen_empty_udata_cb(void)
+static void gen_empty_udata_cb(void (*gen_helper)(TCGv_i32, TCGv_ptr))
{
TCGv_i32 cpu_index = tcg_temp_ebb_new_i32();
TCGv_ptr udata = tcg_temp_ebb_new_ptr();
@@ -106,12 +110,22 @@ static void gen_empty_udata_cb(void)
tcg_gen_movi_ptr(udata, 0);
tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
- gen_helper_plugin_vcpu_udata_cb(cpu_index, udata);
+ gen_helper(cpu_index, udata);
tcg_temp_free_ptr(udata);
tcg_temp_free_i32(cpu_index);
}
+static void gen_empty_udata_cb_no_wg(void)
+{
+ gen_empty_udata_cb(gen_helper_plugin_vcpu_udata_cb_no_wg);
+}
+
+static void gen_empty_udata_cb_no_rwg(void)
+{
+ gen_empty_udata_cb(gen_helper_plugin_vcpu_udata_cb_no_rwg);
+}
+
/*
* For now we only support addi_i64.
* When we support more ops, we can generate one empty inline cb for each.
@@ -192,7 +206,8 @@ static void plugin_gen_empty_callback(enum plugin_gen_from from)
gen_empty_mem_helper);
/* fall through */
case PLUGIN_GEN_FROM_TB:
- gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb);
+ gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb_no_rwg);
+ gen_wrapped(from, PLUGIN_GEN_CB_UDATA_R, gen_empty_udata_cb_no_wg);
gen_wrapped(from, PLUGIN_GEN_CB_INLINE, gen_empty_inline_cb);
break;
default:
@@ -588,6 +603,12 @@ static void plugin_gen_tb_udata(const struct qemu_plugin_tb *ptb,
inject_udata_cb(ptb->cbs[PLUGIN_CB_REGULAR], begin_op);
}
+static void plugin_gen_tb_udata_r(const struct qemu_plugin_tb *ptb,
+ TCGOp *begin_op)
+{
+ inject_udata_cb(ptb->cbs[PLUGIN_CB_REGULAR_R], begin_op);
+}
+
static void plugin_gen_tb_inline(const struct qemu_plugin_tb *ptb,
TCGOp *begin_op)
{
@@ -602,6 +623,14 @@ static void plugin_gen_insn_udata(const struct qemu_plugin_tb *ptb,
inject_udata_cb(insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR], begin_op);
}
+static void plugin_gen_insn_udata_r(const struct qemu_plugin_tb *ptb,
+ TCGOp *begin_op, int insn_idx)
+{
+ struct qemu_plugin_insn *insn = g_ptr_array_index(ptb->insns, insn_idx);
+
+ inject_udata_cb(insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR_R], begin_op);
+}
+
static void plugin_gen_insn_inline(const struct qemu_plugin_tb *ptb,
TCGOp *begin_op, int insn_idx)
{
@@ -721,6 +750,9 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
case PLUGIN_GEN_CB_UDATA:
plugin_gen_tb_udata(plugin_tb, op);
break;
+ case PLUGIN_GEN_CB_UDATA_R:
+ plugin_gen_tb_udata_r(plugin_tb, op);
+ break;
case PLUGIN_GEN_CB_INLINE:
plugin_gen_tb_inline(plugin_tb, op);
break;
@@ -737,6 +769,9 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
case PLUGIN_GEN_CB_UDATA:
plugin_gen_insn_udata(plugin_tb, op, insn_idx);
break;
+ case PLUGIN_GEN_CB_UDATA_R:
+ plugin_gen_insn_udata_r(plugin_tb, op, insn_idx);
+ break;
case PLUGIN_GEN_CB_INLINE:
plugin_gen_insn_inline(plugin_tb, op, insn_idx);
break;
diff --git a/plugins/api.c b/plugins/api.c
index 116b8bd603c..54df72c1c00 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -89,7 +89,11 @@ void qemu_plugin_register_vcpu_tb_exec_cb(struct qemu_plugin_tb *tb,
void *udata)
{
if (!tb->mem_only) {
- plugin_register_dyn_cb__udata(&tb->cbs[PLUGIN_CB_REGULAR],
+ int index = flags == QEMU_PLUGIN_CB_R_REGS ||
+ flags == QEMU_PLUGIN_CB_RW_REGS ?
+ PLUGIN_CB_REGULAR_R : PLUGIN_CB_REGULAR;
+
+ plugin_register_dyn_cb__udata(&tb->cbs[index],
cb, flags, udata);
}
}
@@ -109,7 +113,11 @@ void qemu_plugin_register_vcpu_insn_exec_cb(struct qemu_plugin_insn *insn,
void *udata)
{
if (!insn->mem_only) {
- plugin_register_dyn_cb__udata(&insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR],
+ int index = flags == QEMU_PLUGIN_CB_R_REGS ||
+ flags == QEMU_PLUGIN_CB_RW_REGS ?
+ PLUGIN_CB_REGULAR_R : PLUGIN_CB_REGULAR;
+
+ plugin_register_dyn_cb__udata(&insn->cbs[PLUGIN_CB_INSN][index],
cb, flags, udata);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 17/23] gdbstub: expose api to find registers
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (15 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 16/23] plugins: Use different helpers when reading registers Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 18/23] plugins: add an API to read registers Alex Bennée
` (5 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
Expose an internal API to QEMU to return all the registers for a vCPU.
The list containing the details required to called gdb_read_register().
Based-on: <20231025093128.33116-15-akihiko.odaki@daynix.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-38-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
v3
- rm unused api functions left over
---
include/exec/gdbstub.h | 28 ++++++++++++++++++++++++++++
gdbstub/gdbstub.c | 27 ++++++++++++++++++++++++++-
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index da9ddfe54c5..eb14b91139b 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -111,6 +111,34 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *builder);
*/
const GDBFeature *gdb_find_static_feature(const char *xmlname);
+/**
+ * gdb_read_register() - Read a register associated with a CPU.
+ * @cpu: The CPU associated with the register.
+ * @buf: The buffer that the read register will be appended to.
+ * @reg: The register's number returned by gdb_find_feature_register().
+ *
+ * Return: The number of read bytes.
+ */
+int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
+
+/**
+ * typedef GDBRegDesc - a register description from gdbstub
+ */
+typedef struct {
+ int gdb_reg;
+ const char *name;
+ const char *feature_name;
+} GDBRegDesc;
+
+/**
+ * gdb_get_register_list() - Return list of all registers for CPU
+ * @cpu: The CPU being searched
+ *
+ * Returns a GArray of GDBRegDesc, caller frees array but not the
+ * const strings.
+ */
+GArray *gdb_get_register_list(CPUState *cpu);
+
void gdb_set_stop_cpu(CPUState *cpu);
/* in gdbstub-xml.c, generated by scripts/feature_to_c.py */
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index a55b5e6581a..2909bc8c69f 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -490,7 +490,32 @@ const GDBFeature *gdb_find_static_feature(const char *xmlname)
g_assert_not_reached();
}
-static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
+GArray *gdb_get_register_list(CPUState *cpu)
+{
+ GArray *results = g_array_new(true, true, sizeof(GDBRegDesc));
+
+ /* registers are only available once the CPU is initialised */
+ if (!cpu->gdb_regs) {
+ return results;
+ }
+
+ for (int f = 0; f < cpu->gdb_regs->len; f++) {
+ GDBRegisterState *r = &g_array_index(cpu->gdb_regs, GDBRegisterState, f);
+ for (int i = 0; i < r->feature->num_regs; i++) {
+ const char *name = r->feature->regs[i];
+ GDBRegDesc desc = {
+ r->base_reg + i,
+ name,
+ r->feature->name
+ };
+ g_array_append_val(results, desc);
+ }
+ }
+
+ return results;
+}
+
+int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
GDBRegisterState *r;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 18/23] plugins: add an API to read registers
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (16 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 17/23] gdbstub: expose api to find registers Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-17 8:01 ` Akihiko Odaki
2024-02-16 16:30 ` [PATCH 19/23] contrib/plugins: fix imatch Alex Bennée
` (4 subsequent siblings)
22 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the get function on
vCPU initialisation or during the translation phase.
We don't expose the reg number to the plugin instead hiding it behind
an opaque handle. This allows for a bit of future proofing should the
internals need to be changed while also being hashed against the
CPUClass so we can handle different register sets per-vCPU in
hetrogenous situations.
Having an internal state within the plugins also allows us to expand
the interface in future (for example providing callbacks on register
change if the translator can track changes).
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
v4
- the get/read_registers functions are now implicitly for current
vCPU only to accidental cpu != current_cpu uses.
---
include/qemu/qemu-plugin.h | 48 +++++++++++++++-
plugins/api.c | 107 +++++++++++++++++++++++++++++++++++
plugins/qemu-plugins.symbols | 2 +
3 files changed, 155 insertions(+), 2 deletions(-)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 93981f8f89f..3b6b18058d2 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugin.h
@@ -11,6 +11,7 @@
#ifndef QEMU_QEMU_PLUGIN_H
#define QEMU_QEMU_PLUGIN_H
+#include <glib.h>
#include <inttypes.h>
#include <stdbool.h>
#include <stddef.h>
@@ -229,8 +230,8 @@ struct qemu_plugin_insn;
* @QEMU_PLUGIN_CB_R_REGS: callback reads the CPU's regs
* @QEMU_PLUGIN_CB_RW_REGS: callback reads and writes the CPU's regs
*
- * Note: currently unused, plugins cannot read or change system
- * register state.
+ * Note: currently QEMU_PLUGIN_CB_RW_REGS is unused, plugins cannot change
+ * system register state.
*/
enum qemu_plugin_cb_flags {
QEMU_PLUGIN_CB_NO_REGS,
@@ -707,4 +708,47 @@ uint64_t qemu_plugin_end_code(void);
QEMU_PLUGIN_API
uint64_t qemu_plugin_entry_code(void);
+/** struct qemu_plugin_register - Opaque handle for register access */
+struct qemu_plugin_register;
+
+/**
+ * typedef qemu_plugin_reg_descriptor - register descriptions
+ *
+ * @handle: opaque handle for retrieving value with qemu_plugin_read_register
+ * @name: register name
+ * @feature: optional feature descriptor, can be NULL
+ */
+typedef struct {
+ struct qemu_plugin_register *handle;
+ const char *name;
+ const char *feature;
+} qemu_plugin_reg_descriptor;
+
+/**
+ * qemu_plugin_get_registers() - return register list for current vCPU
+ *
+ * Returns a GArray of qemu_plugin_reg_descriptor or NULL. Caller
+ * frees the array (but not the const strings).
+ *
+ * Should be used from a qemu_plugin_register_vcpu_init_cb() callback
+ * after the vCPU is initialised, i.e. in the vCPU context.
+ */
+GArray *qemu_plugin_get_registers(void);
+
+/**
+ * qemu_plugin_read_register() - read register for current vCPU
+ *
+ * @handle: a @qemu_plugin_reg_handle handle
+ * @buf: A GByteArray for the data owned by the plugin
+ *
+ * This function is only available in a context that register read access is
+ * explicitly requested via the QEMU_PLUGIN_CB_R_REGS flag.
+ *
+ * Returns the size of the read register. The content of @buf is in target byte
+ * order. On failure returns -1
+ */
+int qemu_plugin_read_register(struct qemu_plugin_register *handle,
+ GByteArray *buf);
+
+
#endif /* QEMU_QEMU_PLUGIN_H */
diff --git a/plugins/api.c b/plugins/api.c
index 54df72c1c00..483f04e85e4 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -8,6 +8,7 @@
*
* qemu_plugin_tb
* qemu_plugin_insn
+ * qemu_plugin_register
*
* Which can then be passed back into the API to do additional things.
* As such all the public functions in here are exported in
@@ -35,10 +36,12 @@
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include "qemu/plugin.h"
#include "qemu/log.h"
#include "tcg/tcg.h"
#include "exec/exec-all.h"
+#include "exec/gdbstub.h"
#include "exec/ram_addr.h"
#include "disas/disas.h"
#include "plugin.h"
@@ -410,3 +413,107 @@ uint64_t qemu_plugin_entry_code(void)
#endif
return entry;
}
+
+/*
+ * Register handles
+ *
+ * The plugin infrastructure keeps hold of these internal data
+ * structures which are presented to plugins as opaque handles. They
+ * are global to the system and therefor additions to the hash table
+ * must be protected by the @reg_handle_lock.
+ *
+ * In order to future proof for up-coming heterogeneous work we want
+ * different entries for each CPU type while sharing them in the
+ * common case of multiple cores of the same type.
+ */
+
+static QemuMutex reg_handle_lock;
+
+struct qemu_plugin_register {
+ const char *name;
+ int gdb_reg_num;
+};
+
+static GHashTable *reg_handles; /* hash table of PluginReg */
+
+/* Generate a stable key - would xxhash be overkill? */
+static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
+{
+ uintptr_t key = (uintptr_t) cs->cc;
+ key ^= gdb_regnum;
+ return GUINT_TO_POINTER(key);
+}
+
+/*
+ * Create register handles.
+ *
+ * We need to create a handle for each register so the plugin
+ * infrastructure can call gdbstub to read a register. We also
+ * construct a result array with those handles and some ancillary data
+ * the plugin might find useful.
+ */
+
+static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
+{
+ GArray *find_data = g_array_new(true, true,
+ sizeof(qemu_plugin_reg_descriptor));
+
+ WITH_QEMU_LOCK_GUARD(®_handle_lock) {
+
+ if (!reg_handles) {
+ reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
+ }
+
+ for (int i = 0; i < gdbstub_regs->len; i++) {
+ GDBRegDesc *grd = &g_array_index(gdbstub_regs, GDBRegDesc, i);
+ gpointer key = cpu_plus_reg_to_key(cs, grd->gdb_reg);
+ struct qemu_plugin_register *val = g_hash_table_lookup(reg_handles,
+ key);
+
+ /* skip "un-named" regs */
+ if (!grd->name) {
+ continue;
+ }
+
+ /* Doesn't exist, create one */
+ if (!val) {
+ val = g_new0(struct qemu_plugin_register, 1);
+ val->gdb_reg_num = grd->gdb_reg;
+ val->name = g_intern_string(grd->name);
+
+ g_hash_table_insert(reg_handles, key, val);
+ }
+
+ /* Create a record for the plugin */
+ qemu_plugin_reg_descriptor desc = {
+ .handle = val,
+ .name = val->name,
+ .feature = g_intern_string(grd->feature_name)
+ };
+ g_array_append_val(find_data, desc);
+ }
+ }
+
+ return find_data;
+}
+
+GArray *qemu_plugin_get_registers(void)
+{
+ g_assert(current_cpu);
+
+ g_autoptr(GArray) regs = gdb_get_register_list(current_cpu);
+ return regs->len ? create_register_handles(current_cpu, regs) : NULL;
+}
+
+int qemu_plugin_read_register(struct qemu_plugin_register *reg, GByteArray *buf)
+{
+ g_assert(current_cpu);
+
+ return gdb_read_register(current_cpu, buf, reg->gdb_reg_num);
+}
+
+static void __attribute__((__constructor__)) qemu_api_init(void)
+{
+ qemu_mutex_init(®_handle_lock);
+
+}
diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
index adb67608598..27fe97239be 100644
--- a/plugins/qemu-plugins.symbols
+++ b/plugins/qemu-plugins.symbols
@@ -3,6 +3,7 @@
qemu_plugin_end_code;
qemu_plugin_entry_code;
qemu_plugin_get_hwaddr;
+ qemu_plugin_get_registers;
qemu_plugin_hwaddr_device_name;
qemu_plugin_hwaddr_is_io;
qemu_plugin_hwaddr_phys_addr;
@@ -19,6 +20,7 @@
qemu_plugin_num_vcpus;
qemu_plugin_outs;
qemu_plugin_path_to_binary;
+ qemu_plugin_read_register;
qemu_plugin_register_atexit_cb;
qemu_plugin_register_flush_cb;
qemu_plugin_register_vcpu_exit_cb;
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-16 16:30 ` [PATCH 18/23] plugins: add an API to read registers Alex Bennée
@ 2024-02-17 8:01 ` Akihiko Odaki
2024-02-20 14:14 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Akihiko Odaki @ 2024-02-17 8:01 UTC (permalink / raw)
To: Alex Bennée, qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Cédric Le Goater,
Nicholas Piggin, qemu-s390x, Laurent Vivier, Edgar E. Iglesias,
Daniel Henrique Barboza, Yanan Wang, Palmer Dabbelt,
Marcel Apfelbaum, Brian Cain, Mahmoud Mandour, Alexandre Iooss,
Bin Meng, Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
On 2024/02/17 1:30, Alex Bennée wrote:
> We can only request a list of registers once the vCPU has been
> initialised so the user needs to use either call the get function on
> vCPU initialisation or during the translation phase.
>
> We don't expose the reg number to the plugin instead hiding it behind
> an opaque handle. This allows for a bit of future proofing should the
> internals need to be changed while also being hashed against the
> CPUClass so we can handle different register sets per-vCPU in
> hetrogenous situations.
>
> Having an internal state within the plugins also allows us to expand
> the interface in future (for example providing callbacks on register
> change if the translator can track changes).
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>
> ---
> v4
> - the get/read_registers functions are now implicitly for current
> vCPU only to accidental cpu != current_cpu uses.
> ---
> include/qemu/qemu-plugin.h | 48 +++++++++++++++-
> plugins/api.c | 107 +++++++++++++++++++++++++++++++++++
> plugins/qemu-plugins.symbols | 2 +
> 3 files changed, 155 insertions(+), 2 deletions(-)
>
> diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
> index 93981f8f89f..3b6b18058d2 100644
> --- a/include/qemu/qemu-plugin.h
> +++ b/include/qemu/qemu-plugin.h
> @@ -11,6 +11,7 @@
> #ifndef QEMU_QEMU_PLUGIN_H
> #define QEMU_QEMU_PLUGIN_H
>
> +#include <glib.h>
> #include <inttypes.h>
> #include <stdbool.h>
> #include <stddef.h>
> @@ -229,8 +230,8 @@ struct qemu_plugin_insn;
> * @QEMU_PLUGIN_CB_R_REGS: callback reads the CPU's regs
> * @QEMU_PLUGIN_CB_RW_REGS: callback reads and writes the CPU's regs
> *
> - * Note: currently unused, plugins cannot read or change system
> - * register state.
> + * Note: currently QEMU_PLUGIN_CB_RW_REGS is unused, plugins cannot change
> + * system register state.
> */
> enum qemu_plugin_cb_flags {
> QEMU_PLUGIN_CB_NO_REGS,
> @@ -707,4 +708,47 @@ uint64_t qemu_plugin_end_code(void);
> QEMU_PLUGIN_API
> uint64_t qemu_plugin_entry_code(void);
>
> +/** struct qemu_plugin_register - Opaque handle for register access */
> +struct qemu_plugin_register;
> +
> +/**
> + * typedef qemu_plugin_reg_descriptor - register descriptions
> + *
> + * @handle: opaque handle for retrieving value with qemu_plugin_read_register
> + * @name: register name
> + * @feature: optional feature descriptor, can be NULL
> + */
> +typedef struct {
> + struct qemu_plugin_register *handle;
> + const char *name;
> + const char *feature;
> +} qemu_plugin_reg_descriptor;
> +
> +/**
> + * qemu_plugin_get_registers() - return register list for current vCPU
> + *
> + * Returns a GArray of qemu_plugin_reg_descriptor or NULL. Caller
> + * frees the array (but not the const strings).
> + *
> + * Should be used from a qemu_plugin_register_vcpu_init_cb() callback
> + * after the vCPU is initialised, i.e. in the vCPU context.
> + */
> +GArray *qemu_plugin_get_registers(void);
> +
> +/**
> + * qemu_plugin_read_register() - read register for current vCPU
> + *
> + * @handle: a @qemu_plugin_reg_handle handle
> + * @buf: A GByteArray for the data owned by the plugin
> + *
> + * This function is only available in a context that register read access is
> + * explicitly requested via the QEMU_PLUGIN_CB_R_REGS flag.
> + *
> + * Returns the size of the read register. The content of @buf is in target byte
> + * order. On failure returns -1
> + */
> +int qemu_plugin_read_register(struct qemu_plugin_register *handle,
> + GByteArray *buf);
> +
> +
> #endif /* QEMU_QEMU_PLUGIN_H */
> diff --git a/plugins/api.c b/plugins/api.c
> index 54df72c1c00..483f04e85e4 100644
> --- a/plugins/api.c
> +++ b/plugins/api.c
> @@ -8,6 +8,7 @@
> *
> * qemu_plugin_tb
> * qemu_plugin_insn
> + * qemu_plugin_register
> *
> * Which can then be passed back into the API to do additional things.
> * As such all the public functions in here are exported in
> @@ -35,10 +36,12 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/main-loop.h"
> #include "qemu/plugin.h"
> #include "qemu/log.h"
> #include "tcg/tcg.h"
> #include "exec/exec-all.h"
> +#include "exec/gdbstub.h"
> #include "exec/ram_addr.h"
> #include "disas/disas.h"
> #include "plugin.h"
> @@ -410,3 +413,107 @@ uint64_t qemu_plugin_entry_code(void)
> #endif
> return entry;
> }
> +
> +/*
> + * Register handles
> + *
> + * The plugin infrastructure keeps hold of these internal data
> + * structures which are presented to plugins as opaque handles. They
> + * are global to the system and therefor additions to the hash table
> + * must be protected by the @reg_handle_lock.
> + *
> + * In order to future proof for up-coming heterogeneous work we want
> + * different entries for each CPU type while sharing them in the
> + * common case of multiple cores of the same type.
> + */
> +
> +static QemuMutex reg_handle_lock;
> +
> +struct qemu_plugin_register {
> + const char *name;
> + int gdb_reg_num;
> +};
> +
> +static GHashTable *reg_handles; /* hash table of PluginReg */
> +
> +/* Generate a stable key - would xxhash be overkill? */
> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
> +{
> + uintptr_t key = (uintptr_t) cs->cc;
> + key ^= gdb_regnum;
> + return GUINT_TO_POINTER(key);
> +}
I have pointed out this is theoretically prone to collisions and unsafe.
> +
> +/*
> + * Create register handles.
> + *
> + * We need to create a handle for each register so the plugin
> + * infrastructure can call gdbstub to read a register. We also
> + * construct a result array with those handles and some ancillary data
> + * the plugin might find useful.
> + */
> +
> +static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
> +{
> + GArray *find_data = g_array_new(true, true,
> + sizeof(qemu_plugin_reg_descriptor));
> +
> + WITH_QEMU_LOCK_GUARD(®_handle_lock) {
> +
> + if (!reg_handles) {
> + reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
> + }
> +
> + for (int i = 0; i < gdbstub_regs->len; i++) {
> + GDBRegDesc *grd = &g_array_index(gdbstub_regs, GDBRegDesc, i);
> + gpointer key = cpu_plus_reg_to_key(cs, grd->gdb_reg);
> + struct qemu_plugin_register *val = g_hash_table_lookup(reg_handles,
> + key);
> +
> + /* skip "un-named" regs */
> + if (!grd->name) {
> + continue;
> + }
> +
> + /* Doesn't exist, create one */
> + if (!val) {
> + val = g_new0(struct qemu_plugin_register, 1);
> + val->gdb_reg_num = grd->gdb_reg;
> + val->name = g_intern_string(grd->name);
> +
> + g_hash_table_insert(reg_handles, key, val);
> + }
> +
> + /* Create a record for the plugin */
> + qemu_plugin_reg_descriptor desc = {
> + .handle = val,
> + .name = val->name,
> + .feature = g_intern_string(grd->feature_name)
> + };
> + g_array_append_val(find_data, desc);
> + }
> + }
> +
> + return find_data;
> +}
> +
> +GArray *qemu_plugin_get_registers(void)
> +{
> + g_assert(current_cpu);
> +
> + g_autoptr(GArray) regs = gdb_get_register_list(current_cpu);
> + return regs->len ? create_register_handles(current_cpu, regs) : NULL;
> +}
> +
> +int qemu_plugin_read_register(struct qemu_plugin_register *reg, GByteArray *buf)
> +{
> + g_assert(current_cpu);
> +
> + return gdb_read_register(current_cpu, buf, reg->gdb_reg_num);
> +}
> +
> +static void __attribute__((__constructor__)) qemu_api_init(void)
> +{
> + qemu_mutex_init(®_handle_lock);
> +
> +}
> diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
> index adb67608598..27fe97239be 100644
> --- a/plugins/qemu-plugins.symbols
> +++ b/plugins/qemu-plugins.symbols
> @@ -3,6 +3,7 @@
> qemu_plugin_end_code;
> qemu_plugin_entry_code;
> qemu_plugin_get_hwaddr;
> + qemu_plugin_get_registers;
> qemu_plugin_hwaddr_device_name;
> qemu_plugin_hwaddr_is_io;
> qemu_plugin_hwaddr_phys_addr;
> @@ -19,6 +20,7 @@
> qemu_plugin_num_vcpus;
> qemu_plugin_outs;
> qemu_plugin_path_to_binary;
> + qemu_plugin_read_register;
> qemu_plugin_register_atexit_cb;
> qemu_plugin_register_flush_cb;
> qemu_plugin_register_vcpu_exit_cb;
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-17 8:01 ` Akihiko Odaki
@ 2024-02-20 14:14 ` Alex Bennée
2024-02-21 4:45 ` Akihiko Odaki
0 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-20 14:14 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Akihiko Odaki <akihiko.odaki@daynix.com> writes:
> On 2024/02/17 1:30, Alex Bennée wrote:
>> We can only request a list of registers once the vCPU has been
>> initialised so the user needs to use either call the get function on
>> vCPU initialisation or during the translation phase.
>> We don't expose the reg number to the plugin instead hiding it
>> behind
>> an opaque handle. This allows for a bit of future proofing should the
>> internals need to be changed while also being hashed against the
>> CPUClass so we can handle different register sets per-vCPU in
>> hetrogenous situations.
>> Having an internal state within the plugins also allows us to expand
>> the interface in future (for example providing callbacks on register
>> change if the translator can track changes).
>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
<snip>
>> +/*
>> + * Register handles
>> + *
>> + * The plugin infrastructure keeps hold of these internal data
>> + * structures which are presented to plugins as opaque handles. They
>> + * are global to the system and therefor additions to the hash table
>> + * must be protected by the @reg_handle_lock.
>> + *
>> + * In order to future proof for up-coming heterogeneous work we want
>> + * different entries for each CPU type while sharing them in the
>> + * common case of multiple cores of the same type.
>> + */
>> +
>> +static QemuMutex reg_handle_lock;
>> +
>> +struct qemu_plugin_register {
>> + const char *name;
>> + int gdb_reg_num;
>> +};
>> +
>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>> +
>> +/* Generate a stable key - would xxhash be overkill? */
>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>> +{
>> + uintptr_t key = (uintptr_t) cs->cc;
>> + key ^= gdb_regnum;
>> + return GUINT_TO_POINTER(key);
>> +}
>
> I have pointed out this is theoretically prone to collisions and
> unsafe.
How is it unsafe? The aim is to share handles for the same CPUClass
rather than having a unique handle per register/cpu combo.
Indeed if I add the following:
--8<---------------cut here---------------start------------->8---
plugins/api.c
@@ -482,6 +482,9 @@ static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
val->name = g_intern_string(grd->name);
g_hash_table_insert(reg_handles, key, val);
+ } else {
+ /* make sure its not a clash */
+ g_assert(val->gdb_reg_num == grd->gdb_reg);
}
/* Create a record for the plugin */
modified tests/plugin/insn.c
@@ -46,6 +46,25 @@ typedef struct {
char *disas;
} Instruction;
+/*
+ * Initialise a new vcpu with reading the register list
+ */
+static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index)
+{
+ g_autoptr(GArray) reg_list = qemu_plugin_get_registers();
+ g_autoptr(GByteArray) reg_value = g_byte_array_new();
+
+ if (reg_list) {
+ for (int i = 0; i < reg_list->len; i++) {
+ qemu_plugin_reg_descriptor *rd = &g_array_index(
+ reg_list, qemu_plugin_reg_descriptor, i);
+ int count = qemu_plugin_read_register(rd->handle, reg_value);
+ g_assert(count > 0);
+ }
+ }
+}
+
+
static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata)
{
unsigned int i = cpu_index % MAX_CPUS;
@@ -212,6 +231,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
sizes = g_array_new(true, true, sizeof(unsigned long));
}
+ /* Register init, translation block and exit callbacks */
+ qemu_plugin_register_vcpu_init_cb(id, vcpu_init);
qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
return 0;
--8<---------------cut here---------------end--------------->8---
Nothing trips up during check-tcg (after I fixed "gdbstub: Infer number
of core registers from XML" to remove the microblaze check on
cc->gdb_num_core_regs).
>
>> +
>> +/*
>> + * Create register handles.
>> + *
>> + * We need to create a handle for each register so the plugin
>> + * infrastructure can call gdbstub to read a register. We also
>> + * construct a result array with those handles and some ancillary data
>> + * the plugin might find useful.
>> + */
>> +
>> +static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
>> +{
>> + GArray *find_data = g_array_new(true, true,
>> + sizeof(qemu_plugin_reg_descriptor));
>> +
>> + WITH_QEMU_LOCK_GUARD(®_handle_lock) {
>> +
>> + if (!reg_handles) {
>> + reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>> + }
>> +
>> + for (int i = 0; i < gdbstub_regs->len; i++) {
>> + GDBRegDesc *grd = &g_array_index(gdbstub_regs, GDBRegDesc, i);
>> + gpointer key = cpu_plus_reg_to_key(cs, grd->gdb_reg);
>> + struct qemu_plugin_register *val = g_hash_table_lookup(reg_handles,
>> + key);
>> +
>> + /* skip "un-named" regs */
>> + if (!grd->name) {
>> + continue;
>> + }
>> +
>> + /* Doesn't exist, create one */
>> + if (!val) {
>> + val = g_new0(struct qemu_plugin_register, 1);
>> + val->gdb_reg_num = grd->gdb_reg;
>> + val->name = g_intern_string(grd->name);
>> +
>> + g_hash_table_insert(reg_handles, key, val);
>> + }
>> +
>> + /* Create a record for the plugin */
>> + qemu_plugin_reg_descriptor desc = {
>> + .handle = val,
>> + .name = val->name,
>> + .feature = g_intern_string(grd->feature_name)
>> + };
>> + g_array_append_val(find_data, desc);
>> + }
>> + }
>> +
>> + return find_data;
>> +}
>> +
>> +GArray *qemu_plugin_get_registers(void)
>> +{
>> + g_assert(current_cpu);
>> +
>> + g_autoptr(GArray) regs = gdb_get_register_list(current_cpu);
>> + return regs->len ? create_register_handles(current_cpu, regs) : NULL;
>> +}
>> +
>> +int qemu_plugin_read_register(struct qemu_plugin_register *reg, GByteArray *buf)
>> +{
>> + g_assert(current_cpu);
>> +
>> + return gdb_read_register(current_cpu, buf, reg->gdb_reg_num);
>> +}
>> +
>> +static void __attribute__((__constructor__)) qemu_api_init(void)
>> +{
>> + qemu_mutex_init(®_handle_lock);
>> +
>> +}
>> diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
>> index adb67608598..27fe97239be 100644
>> --- a/plugins/qemu-plugins.symbols
>> +++ b/plugins/qemu-plugins.symbols
>> @@ -3,6 +3,7 @@
>> qemu_plugin_end_code;
>> qemu_plugin_entry_code;
>> qemu_plugin_get_hwaddr;
>> + qemu_plugin_get_registers;
>> qemu_plugin_hwaddr_device_name;
>> qemu_plugin_hwaddr_is_io;
>> qemu_plugin_hwaddr_phys_addr;
>> @@ -19,6 +20,7 @@
>> qemu_plugin_num_vcpus;
>> qemu_plugin_outs;
>> qemu_plugin_path_to_binary;
>> + qemu_plugin_read_register;
>> qemu_plugin_register_atexit_cb;
>> qemu_plugin_register_flush_cb;
>> qemu_plugin_register_vcpu_exit_cb;
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-20 14:14 ` Alex Bennée
@ 2024-02-21 4:45 ` Akihiko Odaki
2024-02-21 10:02 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Akihiko Odaki @ 2024-02-21 4:45 UTC (permalink / raw)
To: Alex Bennée
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
On 2024/02/20 23:14, Alex Bennée wrote:
> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>
>> On 2024/02/17 1:30, Alex Bennée wrote:
>>> We can only request a list of registers once the vCPU has been
>>> initialised so the user needs to use either call the get function on
>>> vCPU initialisation or during the translation phase.
>>> We don't expose the reg number to the plugin instead hiding it
>>> behind
>>> an opaque handle. This allows for a bit of future proofing should the
>>> internals need to be changed while also being hashed against the
>>> CPUClass so we can handle different register sets per-vCPU in
>>> hetrogenous situations.
>>> Having an internal state within the plugins also allows us to expand
>>> the interface in future (for example providing callbacks on register
>>> change if the translator can track changes).
>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> <snip>
>>> +/*
>>> + * Register handles
>>> + *
>>> + * The plugin infrastructure keeps hold of these internal data
>>> + * structures which are presented to plugins as opaque handles. They
>>> + * are global to the system and therefor additions to the hash table
>>> + * must be protected by the @reg_handle_lock.
>>> + *
>>> + * In order to future proof for up-coming heterogeneous work we want
>>> + * different entries for each CPU type while sharing them in the
>>> + * common case of multiple cores of the same type.
>>> + */
>>> +
>>> +static QemuMutex reg_handle_lock;
>>> +
>>> +struct qemu_plugin_register {
>>> + const char *name;
>>> + int gdb_reg_num;
>>> +};
>>> +
>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>> +
>>> +/* Generate a stable key - would xxhash be overkill? */
>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>> +{
>>> + uintptr_t key = (uintptr_t) cs->cc;
>>> + key ^= gdb_regnum;
>>> + return GUINT_TO_POINTER(key);
>>> +}
>>
>> I have pointed out this is theoretically prone to collisions and
>> unsafe.
>
> How is it unsafe? The aim is to share handles for the same CPUClass
> rather than having a unique handle per register/cpu combo.
THe intention is legitimate, but the implementation is not safe. It
assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
guarantee. The key of GHashTable must be unique; generating hashes of
keys should be done with hash_func given to g_hash_table_new().
>
> Indeed if I add the following:
>
> --8<---------------cut here---------------start------------->8---
> plugins/api.c
> @@ -482,6 +482,9 @@ static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
> val->name = g_intern_string(grd->name);
>
> g_hash_table_insert(reg_handles, key, val);
> + } else {
> + /* make sure its not a clash */
> + g_assert(val->gdb_reg_num == grd->gdb_reg);
> }
>
> /* Create a record for the plugin */
> modified tests/plugin/insn.c
> @@ -46,6 +46,25 @@ typedef struct {
> char *disas;
> } Instruction;
>
> +/*
> + * Initialise a new vcpu with reading the register list
> + */
> +static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index)
> +{
> + g_autoptr(GArray) reg_list = qemu_plugin_get_registers();
> + g_autoptr(GByteArray) reg_value = g_byte_array_new();
> +
> + if (reg_list) {
> + for (int i = 0; i < reg_list->len; i++) {
> + qemu_plugin_reg_descriptor *rd = &g_array_index(
> + reg_list, qemu_plugin_reg_descriptor, i);
> + int count = qemu_plugin_read_register(rd->handle, reg_value);
> + g_assert(count > 0);
> + }
> + }
> +}
> +
> +
> static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata)
> {
> unsigned int i = cpu_index % MAX_CPUS;
> @@ -212,6 +231,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
> sizes = g_array_new(true, true, sizeof(unsigned long));
> }
>
> + /* Register init, translation block and exit callbacks */
> + qemu_plugin_register_vcpu_init_cb(id, vcpu_init);
> qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
> qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
> return 0;
> --8<---------------cut here---------------end--------------->8---
>
> Nothing trips up during check-tcg (after I fixed "gdbstub: Infer number
> of core registers from XML" to remove the microblaze check on
> cc->gdb_num_core_regs).
>
>>
>>> +
>>> +/*
>>> + * Create register handles.
>>> + *
>>> + * We need to create a handle for each register so the plugin
>>> + * infrastructure can call gdbstub to read a register. We also
>>> + * construct a result array with those handles and some ancillary data
>>> + * the plugin might find useful.
>>> + */
>>> +
>>> +static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
>>> +{
>>> + GArray *find_data = g_array_new(true, true,
>>> + sizeof(qemu_plugin_reg_descriptor));
>>> +
>>> + WITH_QEMU_LOCK_GUARD(®_handle_lock) {
>>> +
>>> + if (!reg_handles) {
>>> + reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>>> + }
>>> +
>>> + for (int i = 0; i < gdbstub_regs->len; i++) {
>>> + GDBRegDesc *grd = &g_array_index(gdbstub_regs, GDBRegDesc, i);
>>> + gpointer key = cpu_plus_reg_to_key(cs, grd->gdb_reg);
>>> + struct qemu_plugin_register *val = g_hash_table_lookup(reg_handles,
>>> + key);
>>> +
>>> + /* skip "un-named" regs */
>>> + if (!grd->name) {
>>> + continue;
>>> + }
>>> +
>>> + /* Doesn't exist, create one */
>>> + if (!val) {
>>> + val = g_new0(struct qemu_plugin_register, 1);
>>> + val->gdb_reg_num = grd->gdb_reg;
>>> + val->name = g_intern_string(grd->name);
>>> +
>>> + g_hash_table_insert(reg_handles, key, val);
>>> + }
>>> +
>>> + /* Create a record for the plugin */
>>> + qemu_plugin_reg_descriptor desc = {
>>> + .handle = val,
>>> + .name = val->name,
>>> + .feature = g_intern_string(grd->feature_name)
>>> + };
>>> + g_array_append_val(find_data, desc);
>>> + }
>>> + }
>>> +
>>> + return find_data;
>>> +}
>>> +
>>> +GArray *qemu_plugin_get_registers(void)
>>> +{
>>> + g_assert(current_cpu);
>>> +
>>> + g_autoptr(GArray) regs = gdb_get_register_list(current_cpu);
>>> + return regs->len ? create_register_handles(current_cpu, regs) : NULL;
>>> +}
>>> +
>>> +int qemu_plugin_read_register(struct qemu_plugin_register *reg, GByteArray *buf)
>>> +{
>>> + g_assert(current_cpu);
>>> +
>>> + return gdb_read_register(current_cpu, buf, reg->gdb_reg_num);
>>> +}
>>> +
>>> +static void __attribute__((__constructor__)) qemu_api_init(void)
>>> +{
>>> + qemu_mutex_init(®_handle_lock);
>>> +
>>> +}
>>> diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols
>>> index adb67608598..27fe97239be 100644
>>> --- a/plugins/qemu-plugins.symbols
>>> +++ b/plugins/qemu-plugins.symbols
>>> @@ -3,6 +3,7 @@
>>> qemu_plugin_end_code;
>>> qemu_plugin_entry_code;
>>> qemu_plugin_get_hwaddr;
>>> + qemu_plugin_get_registers;
>>> qemu_plugin_hwaddr_device_name;
>>> qemu_plugin_hwaddr_is_io;
>>> qemu_plugin_hwaddr_phys_addr;
>>> @@ -19,6 +20,7 @@
>>> qemu_plugin_num_vcpus;
>>> qemu_plugin_outs;
>>> qemu_plugin_path_to_binary;
>>> + qemu_plugin_read_register;
>>> qemu_plugin_register_atexit_cb;
>>> qemu_plugin_register_flush_cb;
>>> qemu_plugin_register_vcpu_exit_cb;
>
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-21 4:45 ` Akihiko Odaki
@ 2024-02-21 10:02 ` Alex Bennée
2024-02-21 10:11 ` Akihiko Odaki
0 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-21 10:02 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Akihiko Odaki <akihiko.odaki@daynix.com> writes:
> On 2024/02/20 23:14, Alex Bennée wrote:
>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>
>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>> We can only request a list of registers once the vCPU has been
>>>> initialised so the user needs to use either call the get function on
>>>> vCPU initialisation or during the translation phase.
>>>> We don't expose the reg number to the plugin instead hiding it
>>>> behind
>>>> an opaque handle. This allows for a bit of future proofing should the
>>>> internals need to be changed while also being hashed against the
>>>> CPUClass so we can handle different register sets per-vCPU in
>>>> hetrogenous situations.
>>>> Having an internal state within the plugins also allows us to expand
>>>> the interface in future (for example providing callbacks on register
>>>> change if the translator can track changes).
>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> <snip>
>>>> +/*
>>>> + * Register handles
>>>> + *
>>>> + * The plugin infrastructure keeps hold of these internal data
>>>> + * structures which are presented to plugins as opaque handles. They
>>>> + * are global to the system and therefor additions to the hash table
>>>> + * must be protected by the @reg_handle_lock.
>>>> + *
>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>> + * different entries for each CPU type while sharing them in the
>>>> + * common case of multiple cores of the same type.
>>>> + */
>>>> +
>>>> +static QemuMutex reg_handle_lock;
>>>> +
>>>> +struct qemu_plugin_register {
>>>> + const char *name;
>>>> + int gdb_reg_num;
>>>> +};
>>>> +
>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>> +
>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>> +{
>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>> + key ^= gdb_regnum;
>>>> + return GUINT_TO_POINTER(key);
>>>> +}
>>>
>>> I have pointed out this is theoretically prone to collisions and
>>> unsafe.
>> How is it unsafe? The aim is to share handles for the same CPUClass
>> rather than having a unique handle per register/cpu combo.
>
> THe intention is legitimate, but the implementation is not safe. It
> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
> guarantee. The key of GHashTable must be unique; generating hashes of
> keys should be done with hash_func given to g_hash_table_new().
This isn't a hash its a non-unique key. It is however unique for
the same register on the same class of CPU so for each vCPU in a system
can share the same opaque handles.
The hashing is done internally by glib. We would assert if there was a
duplicate key referring to a different register.
I'm unsure what you want here? Do you have a suggestion for the key
generation algorithm? As the comment notes I did consider a more complex
mixing algorithm using xxhash but that wouldn't guarantee no clash
either.
>
>> Indeed if I add the following:
>> --8<---------------cut here---------------start------------->8---
>> plugins/api.c
>> @@ -482,6 +482,9 @@ static GArray *create_register_handles(CPUState *cs, GArray *gdbstub_regs)
>> val->name = g_intern_string(grd->name);
>> g_hash_table_insert(reg_handles, key, val);
>> + } else {
>> + /* make sure its not a clash */
>> + g_assert(val->gdb_reg_num == grd->gdb_reg);
>> }
>> /* Create a record for the plugin */
>> modified tests/plugin/insn.c
>> @@ -46,6 +46,25 @@ typedef struct {
>> char *disas;
>> } Instruction;
>> +/*
>> + * Initialise a new vcpu with reading the register list
>> + */
>> +static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index)
>> +{
>> + g_autoptr(GArray) reg_list = qemu_plugin_get_registers();
>> + g_autoptr(GByteArray) reg_value = g_byte_array_new();
>> +
>> + if (reg_list) {
>> + for (int i = 0; i < reg_list->len; i++) {
>> + qemu_plugin_reg_descriptor *rd = &g_array_index(
>> + reg_list, qemu_plugin_reg_descriptor, i);
>> + int count = qemu_plugin_read_register(rd->handle, reg_value);
>> + g_assert(count > 0);
>> + }
>> + }
>> +}
>> +
>> +
>> static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata)
>> {
>> unsigned int i = cpu_index % MAX_CPUS;
>> @@ -212,6 +231,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
>> sizes = g_array_new(true, true, sizeof(unsigned long));
>> }
>> + /* Register init, translation block and exit callbacks */
>> + qemu_plugin_register_vcpu_init_cb(id, vcpu_init);
>> qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
>> qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
>> return 0;
>> --8<---------------cut here---------------end--------------->8---
>> Nothing trips up during check-tcg (after I fixed "gdbstub: Infer
>> number
>> of core registers from XML" to remove the microblaze check on
>> cc->gdb_num_core_regs).
<snip>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-21 10:02 ` Alex Bennée
@ 2024-02-21 10:11 ` Akihiko Odaki
2024-02-21 14:14 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Akihiko Odaki @ 2024-02-21 10:11 UTC (permalink / raw)
To: Alex Bennée
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
On 2024/02/21 19:02, Alex Bennée wrote:
> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>
>> On 2024/02/20 23:14, Alex Bennée wrote:
>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>
>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>> We can only request a list of registers once the vCPU has been
>>>>> initialised so the user needs to use either call the get function on
>>>>> vCPU initialisation or during the translation phase.
>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>> behind
>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>> internals need to be changed while also being hashed against the
>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>> hetrogenous situations.
>>>>> Having an internal state within the plugins also allows us to expand
>>>>> the interface in future (for example providing callbacks on register
>>>>> change if the translator can track changes).
>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>> <snip>
>>>>> +/*
>>>>> + * Register handles
>>>>> + *
>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>> + * are global to the system and therefor additions to the hash table
>>>>> + * must be protected by the @reg_handle_lock.
>>>>> + *
>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>> + * different entries for each CPU type while sharing them in the
>>>>> + * common case of multiple cores of the same type.
>>>>> + */
>>>>> +
>>>>> +static QemuMutex reg_handle_lock;
>>>>> +
>>>>> +struct qemu_plugin_register {
>>>>> + const char *name;
>>>>> + int gdb_reg_num;
>>>>> +};
>>>>> +
>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>> +
>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>> +{
>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>> + key ^= gdb_regnum;
>>>>> + return GUINT_TO_POINTER(key);
>>>>> +}
>>>>
>>>> I have pointed out this is theoretically prone to collisions and
>>>> unsafe.
>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>> rather than having a unique handle per register/cpu combo.
>>
>> THe intention is legitimate, but the implementation is not safe. It
>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>> guarantee. The key of GHashTable must be unique; generating hashes of
>> keys should be done with hash_func given to g_hash_table_new().
>
> This isn't a hash its a non-unique key. It is however unique for
> the same register on the same class of CPU so for each vCPU in a system
> can share the same opaque handles.
>
> The hashing is done internally by glib. We would assert if there was a
> duplicate key referring to a different register.
>
> I'm unsure what you want here? Do you have a suggestion for the key
> generation algorithm? As the comment notes I did consider a more complex
> mixing algorithm using xxhash but that wouldn't guarantee no clash
> either.
I suggest using a struct that holds both of cs->cc and gdb_regnum, and
pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-21 10:11 ` Akihiko Odaki
@ 2024-02-21 14:14 ` Alex Bennée
2024-02-22 6:37 ` Akihiko Odaki
0 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-21 14:14 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Akihiko Odaki <akihiko.odaki@daynix.com> writes:
> On 2024/02/21 19:02, Alex Bennée wrote:
>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>
>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>
>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>> We can only request a list of registers once the vCPU has been
>>>>>> initialised so the user needs to use either call the get function on
>>>>>> vCPU initialisation or during the translation phase.
>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>> behind
>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>> internals need to be changed while also being hashed against the
>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>> hetrogenous situations.
>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>> the interface in future (for example providing callbacks on register
>>>>>> change if the translator can track changes).
>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>> <snip>
>>>>>> +/*
>>>>>> + * Register handles
>>>>>> + *
>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>> + *
>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>> + * common case of multiple cores of the same type.
>>>>>> + */
>>>>>> +
>>>>>> +static QemuMutex reg_handle_lock;
>>>>>> +
>>>>>> +struct qemu_plugin_register {
>>>>>> + const char *name;
>>>>>> + int gdb_reg_num;
>>>>>> +};
>>>>>> +
>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>> +
>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>> +{
>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>> + key ^= gdb_regnum;
>>>>>> + return GUINT_TO_POINTER(key);
>>>>>> +}
>>>>>
>>>>> I have pointed out this is theoretically prone to collisions and
>>>>> unsafe.
>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>> rather than having a unique handle per register/cpu combo.
>>>
>>> THe intention is legitimate, but the implementation is not safe. It
>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>> keys should be done with hash_func given to g_hash_table_new().
>> This isn't a hash its a non-unique key. It is however unique for
>> the same register on the same class of CPU so for each vCPU in a system
>> can share the same opaque handles.
>> The hashing is done internally by glib. We would assert if there was
>> a
>> duplicate key referring to a different register.
>> I'm unsure what you want here? Do you have a suggestion for the key
>> generation algorithm? As the comment notes I did consider a more complex
>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>> either.
>
> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
We already do:
if (!reg_handles) {
reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
}
But we can't use g_direct_equal with something that exceeds the width of
gpointer as it is a straight equality test of the key. What you are
suggesting requires allocating memory for each key and de-referencing
with a custom GEqualFunc.
This seems overkill for something that as I have said doesn't happen.
The reason it doesn't happen is you will never see two CPUClass
instances so close to each other they share all bits apart from where
gdb_regnum is being xor'd. We could assert that is the case with
something like:
#define MAX_GDBREGS 300
/* Generate a stable key - would xxhash be overkill? */
static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
{
uintptr_t key = (uintptr_t) cs->cc;
qemu_build_assert(sizeof(*cs->cc) >= MAX_GDBREGS);
g_assert(gdb_regnum < MAX_GDBREGS);
key ^= gdb_regnum;
return GUINT_TO_POINTER(key);
}
although MAX_GDBREGS is currently a guess based on aarch64. In practice
though there are so many allocations thing are much farther apart. As we
can see in the one heterogeneous model we support at the moment (the
last 2 CPUs are cortex-r5f's):
./qemu-system-aarch64 -M xlnx-zcu102 -audio none -smp 6 -serial mon:stdio -s -S -smp 6
cpu_common_class_init: k = 0x5565bebf10f0
arm_cpu_initfn: 0x7f32ee0a8360 -> klass = 0x5565bee50e00
aarch64_cpu_instance_init: 0x7f32ee0a8360 -> klass = 0x5565bee50e00
arm_cpu_initfn: 0x7f32ee0be1f0 -> klass = 0x5565bee50e00
aarch64_cpu_instance_init: 0x7f32ee0be1f0 -> klass = 0x5565bee50e00
arm_cpu_initfn: 0x7f32ee0d4080 -> klass = 0x5565bee50e00
aarch64_cpu_instance_init: 0x7f32ee0d4080 -> klass = 0x5565bee50e00
arm_cpu_initfn: 0x7f32ee0e9f10 -> klass = 0x5565bee50e00
aarch64_cpu_instance_init: 0x7f32ee0e9f10 -> klass = 0x5565bee50e00
arm_cpu_initfn: 0x7f32ee0ffda0 -> klass = 0x5565bed0fad0
arm_cpu_initfn: 0x7f32ee115c30 -> klass = 0x5565bed0fad0
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-21 14:14 ` Alex Bennée
@ 2024-02-22 6:37 ` Akihiko Odaki
2024-02-22 10:20 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Akihiko Odaki @ 2024-02-22 6:37 UTC (permalink / raw)
To: Alex Bennée
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
On 2024/02/21 23:14, Alex Bennée wrote:
> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>
>> On 2024/02/21 19:02, Alex Bennée wrote:
>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>
>>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>
>>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>>> We can only request a list of registers once the vCPU has been
>>>>>>> initialised so the user needs to use either call the get function on
>>>>>>> vCPU initialisation or during the translation phase.
>>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>>> behind
>>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>>> internals need to be changed while also being hashed against the
>>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>>> hetrogenous situations.
>>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>>> the interface in future (for example providing callbacks on register
>>>>>>> change if the translator can track changes).
>>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>> <snip>
>>>>>>> +/*
>>>>>>> + * Register handles
>>>>>>> + *
>>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>>> + *
>>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>>> + * common case of multiple cores of the same type.
>>>>>>> + */
>>>>>>> +
>>>>>>> +static QemuMutex reg_handle_lock;
>>>>>>> +
>>>>>>> +struct qemu_plugin_register {
>>>>>>> + const char *name;
>>>>>>> + int gdb_reg_num;
>>>>>>> +};
>>>>>>> +
>>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>>> +
>>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>>> +{
>>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>>> + key ^= gdb_regnum;
>>>>>>> + return GUINT_TO_POINTER(key);
>>>>>>> +}
>>>>>>
>>>>>> I have pointed out this is theoretically prone to collisions and
>>>>>> unsafe.
>>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>>> rather than having a unique handle per register/cpu combo.
>>>>
>>>> THe intention is legitimate, but the implementation is not safe. It
>>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>>> keys should be done with hash_func given to g_hash_table_new().
>>> This isn't a hash its a non-unique key. It is however unique for
>>> the same register on the same class of CPU so for each vCPU in a system
>>> can share the same opaque handles.
>>> The hashing is done internally by glib. We would assert if there was
>>> a
>>> duplicate key referring to a different register.
>>> I'm unsure what you want here? Do you have a suggestion for the key
>>> generation algorithm? As the comment notes I did consider a more complex
>>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>>> either.
>>
>> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
>> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
>
> We already do:
>
> if (!reg_handles) {
> reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
> }
>
> But we can't use g_direct_equal with something that exceeds the width of
> gpointer as it is a straight equality test of the key. What you are
> suggesting requires allocating memory for each key and de-referencing
> with a custom GEqualFunc.
My bad. I wrongly remembered g_direct_equal() and g_direct_hash(). It
indeed seems to need a more complicated solution.
It is possible to write a GEqualFunc and a GHashFunc that consumes a
struct but it is a chore. How about having a two-level GHashTable?
reg_handles will be a GHashTable keyed with cs->cc, and another
GHashTable will be keyed with gdb_regnum.
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-22 6:37 ` Akihiko Odaki
@ 2024-02-22 10:20 ` Alex Bennée
2024-02-22 13:22 ` Akihiko Odaki
0 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-22 10:20 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Akihiko Odaki <akihiko.odaki@daynix.com> writes:
> On 2024/02/21 23:14, Alex Bennée wrote:
>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>
>>> On 2024/02/21 19:02, Alex Bennée wrote:
>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>
>>>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>
>>>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>>>> We can only request a list of registers once the vCPU has been
>>>>>>>> initialised so the user needs to use either call the get function on
>>>>>>>> vCPU initialisation or during the translation phase.
>>>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>>>> behind
>>>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>>>> internals need to be changed while also being hashed against the
>>>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>>>> hetrogenous situations.
>>>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>>>> the interface in future (for example providing callbacks on register
>>>>>>>> change if the translator can track changes).
>>>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>>> <snip>
>>>>>>>> +/*
>>>>>>>> + * Register handles
>>>>>>>> + *
>>>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>>>> + *
>>>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>>>> + * common case of multiple cores of the same type.
>>>>>>>> + */
>>>>>>>> +
>>>>>>>> +static QemuMutex reg_handle_lock;
>>>>>>>> +
>>>>>>>> +struct qemu_plugin_register {
>>>>>>>> + const char *name;
>>>>>>>> + int gdb_reg_num;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>>>> +
>>>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>>>> +{
>>>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>>>> + key ^= gdb_regnum;
>>>>>>>> + return GUINT_TO_POINTER(key);
>>>>>>>> +}
>>>>>>>
>>>>>>> I have pointed out this is theoretically prone to collisions and
>>>>>>> unsafe.
>>>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>>>> rather than having a unique handle per register/cpu combo.
>>>>>
>>>>> THe intention is legitimate, but the implementation is not safe. It
>>>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>>>> keys should be done with hash_func given to g_hash_table_new().
>>>> This isn't a hash its a non-unique key. It is however unique for
>>>> the same register on the same class of CPU so for each vCPU in a system
>>>> can share the same opaque handles.
>>>> The hashing is done internally by glib. We would assert if there was
>>>> a
>>>> duplicate key referring to a different register.
>>>> I'm unsure what you want here? Do you have a suggestion for the key
>>>> generation algorithm? As the comment notes I did consider a more complex
>>>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>>>> either.
>>>
>>> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
>>> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
>> We already do:
>> if (!reg_handles) {
>> reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>> }
>> But we can't use g_direct_equal with something that exceeds the
>> width of
>> gpointer as it is a straight equality test of the key. What you are
>> suggesting requires allocating memory for each key and de-referencing
>> with a custom GEqualFunc.
>
> My bad. I wrongly remembered g_direct_equal() and g_direct_hash(). It
> indeed seems to need a more complicated solution.
>
> It is possible to write a GEqualFunc and a GHashFunc that consumes a
> struct but it is a chore. How about having a two-level GHashTable?
> reg_handles will be a GHashTable keyed with cs->cc, and another
> GHashTable will be keyed with gdb_regnum.
That still seems overkill for a clash that can't happen. What do you
think about the following:
/*
* Generate a stable key shared across CPUs of the same class
*
* In order to future proof for up-coming heterogeneous work we want
* different entries for each CPU type while sharing them in the
* common case of multiple cores of the same type. This makes the
* assumption you won't see two CPUClass pointers that are similar
* enough that the low bits mixed with different registers numbers
* will give you the same key.
*
* The build time assert will fire if CPUClass goes on a sudden diet
* and we assert further down if we detect two keys representing
* different regnums. In practice allocations of CPUClass are much
* farther apart making clashes practically impossible.
*/
static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
{
uintptr_t key = (uintptr_t) cs->cc;
/* this protects some of the assumptions above */
qemu_build_assert(sizeof(*cs->cc) >= 256);
key ^= gdb_regnum;
return GUINT_TO_POINTER(key);
}
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-22 10:20 ` Alex Bennée
@ 2024-02-22 13:22 ` Akihiko Odaki
2024-02-22 17:27 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Akihiko Odaki @ 2024-02-22 13:22 UTC (permalink / raw)
To: Alex Bennée
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
On 2024/02/22 19:20, Alex Bennée wrote:
> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>
>> On 2024/02/21 23:14, Alex Bennée wrote:
>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>
>>>> On 2024/02/21 19:02, Alex Bennée wrote:
>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>
>>>>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>>
>>>>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>>>>> We can only request a list of registers once the vCPU has been
>>>>>>>>> initialised so the user needs to use either call the get function on
>>>>>>>>> vCPU initialisation or during the translation phase.
>>>>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>>>>> behind
>>>>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>>>>> internals need to be changed while also being hashed against the
>>>>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>>>>> hetrogenous situations.
>>>>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>>>>> the interface in future (for example providing callbacks on register
>>>>>>>>> change if the translator can track changes).
>>>>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>>>> <snip>
>>>>>>>>> +/*
>>>>>>>>> + * Register handles
>>>>>>>>> + *
>>>>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>>>>> + *
>>>>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>>>>> + * common case of multiple cores of the same type.
>>>>>>>>> + */
>>>>>>>>> +
>>>>>>>>> +static QemuMutex reg_handle_lock;
>>>>>>>>> +
>>>>>>>>> +struct qemu_plugin_register {
>>>>>>>>> + const char *name;
>>>>>>>>> + int gdb_reg_num;
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>>>>> +
>>>>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>>>>> +{
>>>>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>>>>> + key ^= gdb_regnum;
>>>>>>>>> + return GUINT_TO_POINTER(key);
>>>>>>>>> +}
>>>>>>>>
>>>>>>>> I have pointed out this is theoretically prone to collisions and
>>>>>>>> unsafe.
>>>>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>>>>> rather than having a unique handle per register/cpu combo.
>>>>>>
>>>>>> THe intention is legitimate, but the implementation is not safe. It
>>>>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>>>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>>>>> keys should be done with hash_func given to g_hash_table_new().
>>>>> This isn't a hash its a non-unique key. It is however unique for
>>>>> the same register on the same class of CPU so for each vCPU in a system
>>>>> can share the same opaque handles.
>>>>> The hashing is done internally by glib. We would assert if there was
>>>>> a
>>>>> duplicate key referring to a different register.
>>>>> I'm unsure what you want here? Do you have a suggestion for the key
>>>>> generation algorithm? As the comment notes I did consider a more complex
>>>>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>>>>> either.
>>>>
>>>> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
>>>> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
>>> We already do:
>>> if (!reg_handles) {
>>> reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>>> }
>>> But we can't use g_direct_equal with something that exceeds the
>>> width of
>>> gpointer as it is a straight equality test of the key. What you are
>>> suggesting requires allocating memory for each key and de-referencing
>>> with a custom GEqualFunc.
>>
>> My bad. I wrongly remembered g_direct_equal() and g_direct_hash(). It
>> indeed seems to need a more complicated solution.
>>
>> It is possible to write a GEqualFunc and a GHashFunc that consumes a
>> struct but it is a chore. How about having a two-level GHashTable?
>> reg_handles will be a GHashTable keyed with cs->cc, and another
>> GHashTable will be keyed with gdb_regnum.
>
> That still seems overkill for a clash that can't happen. What do you
> think about the following:
>
> /*
> * Generate a stable key shared across CPUs of the same class
> *
> * In order to future proof for up-coming heterogeneous work we want
> * different entries for each CPU type while sharing them in the
> * common case of multiple cores of the same type. This makes the
> * assumption you won't see two CPUClass pointers that are similar
> * enough that the low bits mixed with different registers numbers
> * will give you the same key.
> *
> * The build time assert will fire if CPUClass goes on a sudden diet
> * and we assert further down if we detect two keys representing
> * different regnums. In practice allocations of CPUClass are much
> * farther apart making clashes practically impossible.
> */
> static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
> {
> uintptr_t key = (uintptr_t) cs->cc;
>
> /* this protects some of the assumptions above */
> qemu_build_assert(sizeof(*cs->cc) >= 256);
>
> key ^= gdb_regnum;
> return GUINT_TO_POINTER(key);
> }
I think the assertion and comments are overkill. Doesn't having a nested
GHashTable save some words you have to wrote for the assumption?
I'm also not quite convinced that the comments and assertions are enough
to say this hack is safe; what if some sort of pointer authentication is
added and shuffles bits? Will this hack be compatible with static and
dynamic checkers we may have in the future?
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-22 13:22 ` Akihiko Odaki
@ 2024-02-22 17:27 ` Alex Bennée
2024-02-23 10:58 ` Akihiko Odaki
0 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-22 17:27 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Akihiko Odaki <akihiko.odaki@daynix.com> writes:
> On 2024/02/22 19:20, Alex Bennée wrote:
>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>
>>> On 2024/02/21 23:14, Alex Bennée wrote:
>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>
>>>>> On 2024/02/21 19:02, Alex Bennée wrote:
>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>
>>>>>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>>>
>>>>>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>>>>>> We can only request a list of registers once the vCPU has been
>>>>>>>>>> initialised so the user needs to use either call the get function on
>>>>>>>>>> vCPU initialisation or during the translation phase.
>>>>>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>>>>>> behind
>>>>>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>>>>>> internals need to be changed while also being hashed against the
>>>>>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>>>>>> hetrogenous situations.
>>>>>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>>>>>> the interface in future (for example providing callbacks on register
>>>>>>>>>> change if the translator can track changes).
>>>>>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>>>>> <snip>
>>>>>>>>>> +/*
>>>>>>>>>> + * Register handles
>>>>>>>>>> + *
>>>>>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>>>>>> + *
>>>>>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>>>>>> + * common case of multiple cores of the same type.
>>>>>>>>>> + */
>>>>>>>>>> +
>>>>>>>>>> +static QemuMutex reg_handle_lock;
>>>>>>>>>> +
>>>>>>>>>> +struct qemu_plugin_register {
>>>>>>>>>> + const char *name;
>>>>>>>>>> + int gdb_reg_num;
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>>>>>> +
>>>>>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>>>>>> +{
>>>>>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>>>>>> + key ^= gdb_regnum;
>>>>>>>>>> + return GUINT_TO_POINTER(key);
>>>>>>>>>> +}
>>>>>>>>>
>>>>>>>>> I have pointed out this is theoretically prone to collisions and
>>>>>>>>> unsafe.
>>>>>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>>>>>> rather than having a unique handle per register/cpu combo.
>>>>>>>
>>>>>>> THe intention is legitimate, but the implementation is not safe. It
>>>>>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>>>>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>>>>>> keys should be done with hash_func given to g_hash_table_new().
>>>>>> This isn't a hash its a non-unique key. It is however unique for
>>>>>> the same register on the same class of CPU so for each vCPU in a system
>>>>>> can share the same opaque handles.
>>>>>> The hashing is done internally by glib. We would assert if there was
>>>>>> a
>>>>>> duplicate key referring to a different register.
>>>>>> I'm unsure what you want here? Do you have a suggestion for the key
>>>>>> generation algorithm? As the comment notes I did consider a more complex
>>>>>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>>>>>> either.
>>>>>
>>>>> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
>>>>> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
>>>> We already do:
>>>> if (!reg_handles) {
>>>> reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>>>> }
>>>> But we can't use g_direct_equal with something that exceeds the
>>>> width of
>>>> gpointer as it is a straight equality test of the key. What you are
>>>> suggesting requires allocating memory for each key and de-referencing
>>>> with a custom GEqualFunc.
>>>
>>> My bad. I wrongly remembered g_direct_equal() and g_direct_hash(). It
>>> indeed seems to need a more complicated solution.
>>>
>>> It is possible to write a GEqualFunc and a GHashFunc that consumes a
>>> struct but it is a chore. How about having a two-level GHashTable?
>>> reg_handles will be a GHashTable keyed with cs->cc, and another
>>> GHashTable will be keyed with gdb_regnum.
>> That still seems overkill for a clash that can't happen. What do you
>> think about the following:
>> /*
>> * Generate a stable key shared across CPUs of the same class
>> *
>> * In order to future proof for up-coming heterogeneous work we want
>> * different entries for each CPU type while sharing them in the
>> * common case of multiple cores of the same type. This makes the
>> * assumption you won't see two CPUClass pointers that are similar
>> * enough that the low bits mixed with different registers numbers
>> * will give you the same key.
>> *
>> * The build time assert will fire if CPUClass goes on a sudden diet
>> * and we assert further down if we detect two keys representing
>> * different regnums. In practice allocations of CPUClass are much
>> * farther apart making clashes practically impossible.
>> */
>> static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>> {
>> uintptr_t key = (uintptr_t) cs->cc;
>> /* this protects some of the assumptions above */
>> qemu_build_assert(sizeof(*cs->cc) >= 256);
>> key ^= gdb_regnum;
>> return GUINT_TO_POINTER(key);
>> }
>
>
> I think the assertion and comments are overkill. Doesn't having a
> nested GHashTable save some words you have to wrote for the
> assumption?
A nested hash table for a single entry is overkill.
> I'm also not quite convinced that the comments and assertions are
> enough to say this hack is safe; what if some sort of pointer
> authentication is added and shuffles bits? Will this hack be
> compatible with static and dynamic checkers we may have in the future?
We are not using the value as a pointer so that should be irrelevant
although generally those bits tend to be at the top of pointers so they
can be masked off.
I'm not sure what we are trying to achieve here. I've got something that
works, doesn't fail any tests and has some guards in for potential
future problems. At the same time I'm not prepared to over-engineer the
solution for a theoretical future problem we haven't got yet.
What about if I just key based of gdb_regnum and we accept that that
might break the one heterogeneous system we model today?
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-22 17:27 ` Alex Bennée
@ 2024-02-23 10:58 ` Akihiko Odaki
2024-02-23 11:44 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Akihiko Odaki @ 2024-02-23 10:58 UTC (permalink / raw)
To: Alex Bennée
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
On 2024/02/23 2:27, Alex Bennée wrote:
> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>
>> On 2024/02/22 19:20, Alex Bennée wrote:
>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>
>>>> On 2024/02/21 23:14, Alex Bennée wrote:
>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>
>>>>>> On 2024/02/21 19:02, Alex Bennée wrote:
>>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>>
>>>>>>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>>>>
>>>>>>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>>>>>>> We can only request a list of registers once the vCPU has been
>>>>>>>>>>> initialised so the user needs to use either call the get function on
>>>>>>>>>>> vCPU initialisation or during the translation phase.
>>>>>>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>>>>>>> behind
>>>>>>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>>>>>>> internals need to be changed while also being hashed against the
>>>>>>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>>>>>>> hetrogenous situations.
>>>>>>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>>>>>>> the interface in future (for example providing callbacks on register
>>>>>>>>>>> change if the translator can track changes).
>>>>>>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>>>>>> <snip>
>>>>>>>>>>> +/*
>>>>>>>>>>> + * Register handles
>>>>>>>>>>> + *
>>>>>>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>>>>>>> + *
>>>>>>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>>>>>>> + * common case of multiple cores of the same type.
>>>>>>>>>>> + */
>>>>>>>>>>> +
>>>>>>>>>>> +static QemuMutex reg_handle_lock;
>>>>>>>>>>> +
>>>>>>>>>>> +struct qemu_plugin_register {
>>>>>>>>>>> + const char *name;
>>>>>>>>>>> + int gdb_reg_num;
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>>>>>>> +
>>>>>>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>>>>>>> +{
>>>>>>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>>>>>>> + key ^= gdb_regnum;
>>>>>>>>>>> + return GUINT_TO_POINTER(key);
>>>>>>>>>>> +}
>>>>>>>>>>
>>>>>>>>>> I have pointed out this is theoretically prone to collisions and
>>>>>>>>>> unsafe.
>>>>>>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>>>>>>> rather than having a unique handle per register/cpu combo.
>>>>>>>>
>>>>>>>> THe intention is legitimate, but the implementation is not safe. It
>>>>>>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>>>>>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>>>>>>> keys should be done with hash_func given to g_hash_table_new().
>>>>>>> This isn't a hash its a non-unique key. It is however unique for
>>>>>>> the same register on the same class of CPU so for each vCPU in a system
>>>>>>> can share the same opaque handles.
>>>>>>> The hashing is done internally by glib. We would assert if there was
>>>>>>> a
>>>>>>> duplicate key referring to a different register.
>>>>>>> I'm unsure what you want here? Do you have a suggestion for the key
>>>>>>> generation algorithm? As the comment notes I did consider a more complex
>>>>>>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>>>>>>> either.
>>>>>>
>>>>>> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
>>>>>> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
>>>>> We already do:
>>>>> if (!reg_handles) {
>>>>> reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>>>>> }
>>>>> But we can't use g_direct_equal with something that exceeds the
>>>>> width of
>>>>> gpointer as it is a straight equality test of the key. What you are
>>>>> suggesting requires allocating memory for each key and de-referencing
>>>>> with a custom GEqualFunc.
>>>>
>>>> My bad. I wrongly remembered g_direct_equal() and g_direct_hash(). It
>>>> indeed seems to need a more complicated solution.
>>>>
>>>> It is possible to write a GEqualFunc and a GHashFunc that consumes a
>>>> struct but it is a chore. How about having a two-level GHashTable?
>>>> reg_handles will be a GHashTable keyed with cs->cc, and another
>>>> GHashTable will be keyed with gdb_regnum.
>>> That still seems overkill for a clash that can't happen. What do you
>>> think about the following:
>>> /*
>>> * Generate a stable key shared across CPUs of the same class
>>> *
>>> * In order to future proof for up-coming heterogeneous work we want
>>> * different entries for each CPU type while sharing them in the
>>> * common case of multiple cores of the same type. This makes the
>>> * assumption you won't see two CPUClass pointers that are similar
>>> * enough that the low bits mixed with different registers numbers
>>> * will give you the same key.
>>> *
>>> * The build time assert will fire if CPUClass goes on a sudden diet
>>> * and we assert further down if we detect two keys representing
>>> * different regnums. In practice allocations of CPUClass are much
>>> * farther apart making clashes practically impossible.
>>> */
>>> static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>> {
>>> uintptr_t key = (uintptr_t) cs->cc;
>>> /* this protects some of the assumptions above */
>>> qemu_build_assert(sizeof(*cs->cc) >= 256);
>>> key ^= gdb_regnum;
>>> return GUINT_TO_POINTER(key);
>>> }
>>
>>
>> I think the assertion and comments are overkill. Doesn't having a
>> nested GHashTable save some words you have to wrote for the
>> assumption?
>
> A nested hash table for a single entry is overkill.
You mean that the first level will be indexed by only one CPUClass (or
few if we support a heterogeneous system).
I think it's still OK though. It's not like we will need more code when
having few entries.
>
>> I'm also not quite convinced that the comments and assertions are
>> enough to say this hack is safe; what if some sort of pointer
>> authentication is added and shuffles bits? Will this hack be
>> compatible with static and dynamic checkers we may have in the future?
>
> We are not using the value as a pointer so that should be irrelevant
> although generally those bits tend to be at the top of pointers so they
> can be masked off.
>
> I'm not sure what we are trying to achieve here. I've got something that
> works, doesn't fail any tests and has some guards in for potential
> future problems. At the same time I'm not prepared to over-engineer the
> solution for a theoretical future problem we haven't got yet.
>
> What about if I just key based of gdb_regnum and we accept that that
> might break the one heterogeneous system we model today?
>
That's the best option in my opinion. gdbstub won't work well with such
a system anyway, and fixing it will need something similar to
GHashTable. But if I would fix gdbstub for a heterogeneous system, I
would add a field to CPUClass instead of having a GHashTable keyed with
tuples of CPUClass pointers and register numbers. It should be fine
considering that CPUState already has gdbstub-specific fields like gdb_regs.
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-23 10:58 ` Akihiko Odaki
@ 2024-02-23 11:44 ` Alex Bennée
2024-02-23 16:24 ` Alex Bennée
0 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-23 11:44 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Akihiko Odaki <akihiko.odaki@daynix.com> writes:
> On 2024/02/23 2:27, Alex Bennée wrote:
>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>
>>> On 2024/02/22 19:20, Alex Bennée wrote:
>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>
>>>>> On 2024/02/21 23:14, Alex Bennée wrote:
>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>
>>>>>>> On 2024/02/21 19:02, Alex Bennée wrote:
>>>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>>>
>>>>>>>>> On 2024/02/20 23:14, Alex Bennée wrote:
>>>>>>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
>>>>>>>>>>
>>>>>>>>>>> On 2024/02/17 1:30, Alex Bennée wrote:
>>>>>>>>>>>> We can only request a list of registers once the vCPU has been
>>>>>>>>>>>> initialised so the user needs to use either call the get function on
>>>>>>>>>>>> vCPU initialisation or during the translation phase.
>>>>>>>>>>>> We don't expose the reg number to the plugin instead hiding it
>>>>>>>>>>>> behind
>>>>>>>>>>>> an opaque handle. This allows for a bit of future proofing should the
>>>>>>>>>>>> internals need to be changed while also being hashed against the
>>>>>>>>>>>> CPUClass so we can handle different register sets per-vCPU in
>>>>>>>>>>>> hetrogenous situations.
>>>>>>>>>>>> Having an internal state within the plugins also allows us to expand
>>>>>>>>>>>> the interface in future (for example providing callbacks on register
>>>>>>>>>>>> change if the translator can track changes).
>>>>>>>>>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
>>>>>>>>>>>> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
>>>>>>>>>>>> Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
>>>>>>>>>>>> Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
>>>>>>>>>>>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>>>>>>>>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>>>>>>> <snip>
>>>>>>>>>>>> +/*
>>>>>>>>>>>> + * Register handles
>>>>>>>>>>>> + *
>>>>>>>>>>>> + * The plugin infrastructure keeps hold of these internal data
>>>>>>>>>>>> + * structures which are presented to plugins as opaque handles. They
>>>>>>>>>>>> + * are global to the system and therefor additions to the hash table
>>>>>>>>>>>> + * must be protected by the @reg_handle_lock.
>>>>>>>>>>>> + *
>>>>>>>>>>>> + * In order to future proof for up-coming heterogeneous work we want
>>>>>>>>>>>> + * different entries for each CPU type while sharing them in the
>>>>>>>>>>>> + * common case of multiple cores of the same type.
>>>>>>>>>>>> + */
>>>>>>>>>>>> +
>>>>>>>>>>>> +static QemuMutex reg_handle_lock;
>>>>>>>>>>>> +
>>>>>>>>>>>> +struct qemu_plugin_register {
>>>>>>>>>>>> + const char *name;
>>>>>>>>>>>> + int gdb_reg_num;
>>>>>>>>>>>> +};
>>>>>>>>>>>> +
>>>>>>>>>>>> +static GHashTable *reg_handles; /* hash table of PluginReg */
>>>>>>>>>>>> +
>>>>>>>>>>>> +/* Generate a stable key - would xxhash be overkill? */
>>>>>>>>>>>> +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>>>>>>>>>> +{
>>>>>>>>>>>> + uintptr_t key = (uintptr_t) cs->cc;
>>>>>>>>>>>> + key ^= gdb_regnum;
>>>>>>>>>>>> + return GUINT_TO_POINTER(key);
>>>>>>>>>>>> +}
>>>>>>>>>>>
>>>>>>>>>>> I have pointed out this is theoretically prone to collisions and
>>>>>>>>>>> unsafe.
>>>>>>>>>> How is it unsafe? The aim is to share handles for the same CPUClass
>>>>>>>>>> rather than having a unique handle per register/cpu combo.
>>>>>>>>>
>>>>>>>>> THe intention is legitimate, but the implementation is not safe. It
>>>>>>>>> assumes (uintptr)cs->cc ^ gdb_regnum is unique, but there is no such
>>>>>>>>> guarantee. The key of GHashTable must be unique; generating hashes of
>>>>>>>>> keys should be done with hash_func given to g_hash_table_new().
>>>>>>>> This isn't a hash its a non-unique key. It is however unique for
>>>>>>>> the same register on the same class of CPU so for each vCPU in a system
>>>>>>>> can share the same opaque handles.
>>>>>>>> The hashing is done internally by glib. We would assert if there was
>>>>>>>> a
>>>>>>>> duplicate key referring to a different register.
>>>>>>>> I'm unsure what you want here? Do you have a suggestion for the key
>>>>>>>> generation algorithm? As the comment notes I did consider a more complex
>>>>>>>> mixing algorithm using xxhash but that wouldn't guarantee no clash
>>>>>>>> either.
>>>>>>>
>>>>>>> I suggest using a struct that holds both of cs->cc and gdb_regnum, and
>>>>>>> pass g_direct_equal() and g_direct_hash() to g_hash_table_new().
>>>>>> We already do:
>>>>>> if (!reg_handles) {
>>>>>> reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal);
>>>>>> }
>>>>>> But we can't use g_direct_equal with something that exceeds the
>>>>>> width of
>>>>>> gpointer as it is a straight equality test of the key. What you are
>>>>>> suggesting requires allocating memory for each key and de-referencing
>>>>>> with a custom GEqualFunc.
>>>>>
>>>>> My bad. I wrongly remembered g_direct_equal() and g_direct_hash(). It
>>>>> indeed seems to need a more complicated solution.
>>>>>
>>>>> It is possible to write a GEqualFunc and a GHashFunc that consumes a
>>>>> struct but it is a chore. How about having a two-level GHashTable?
>>>>> reg_handles will be a GHashTable keyed with cs->cc, and another
>>>>> GHashTable will be keyed with gdb_regnum.
>>>> That still seems overkill for a clash that can't happen. What do you
>>>> think about the following:
>>>> /*
>>>> * Generate a stable key shared across CPUs of the same class
>>>> *
>>>> * In order to future proof for up-coming heterogeneous work we want
>>>> * different entries for each CPU type while sharing them in the
>>>> * common case of multiple cores of the same type. This makes the
>>>> * assumption you won't see two CPUClass pointers that are similar
>>>> * enough that the low bits mixed with different registers numbers
>>>> * will give you the same key.
>>>> *
>>>> * The build time assert will fire if CPUClass goes on a sudden diet
>>>> * and we assert further down if we detect two keys representing
>>>> * different regnums. In practice allocations of CPUClass are much
>>>> * farther apart making clashes practically impossible.
>>>> */
>>>> static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum)
>>>> {
>>>> uintptr_t key = (uintptr_t) cs->cc;
>>>> /* this protects some of the assumptions above */
>>>> qemu_build_assert(sizeof(*cs->cc) >= 256);
>>>> key ^= gdb_regnum;
>>>> return GUINT_TO_POINTER(key);
>>>> }
>>>
>>>
>>> I think the assertion and comments are overkill. Doesn't having a
>>> nested GHashTable save some words you have to wrote for the
>>> assumption?
>> A nested hash table for a single entry is overkill.
>
> You mean that the first level will be indexed by only one CPUClass (or
> few if we support a heterogeneous system).
>
> I think it's still OK though. It's not like we will need more code
> when having few entries.
>
>>
>>> I'm also not quite convinced that the comments and assertions are
>>> enough to say this hack is safe; what if some sort of pointer
>>> authentication is added and shuffles bits? Will this hack be
>>> compatible with static and dynamic checkers we may have in the future?
>> We are not using the value as a pointer so that should be irrelevant
>> although generally those bits tend to be at the top of pointers so they
>> can be masked off.
>> I'm not sure what we are trying to achieve here. I've got something
>> that
>> works, doesn't fail any tests and has some guards in for potential
>> future problems. At the same time I'm not prepared to over-engineer the
>> solution for a theoretical future problem we haven't got yet.
>> What about if I just key based of gdb_regnum and we accept that that
>> might break the one heterogeneous system we model today?
>>
>
> That's the best option in my opinion. gdbstub won't work well with
> such a system anyway, and fixing it will need something similar to
> GHashTable. But if I would fix gdbstub for a heterogeneous system, I
> would add a field to CPUClass instead of having a GHashTable keyed
> with tuples of CPUClass pointers and register numbers. It should be
> fine considering that CPUState already has gdbstub-specific fields
> like gdb_regs.
It would be nice to move all register code into CPUClass to avoid
repeating ourselves but I suspect that is quite an invasive change for a
later series. Currently all the CPUClass values are set on init and
shouldn't really be changed after that otherwise we'll have to start
messing with locking.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 18/23] plugins: add an API to read registers
2024-02-23 11:44 ` Alex Bennée
@ 2024-02-23 16:24 ` Alex Bennée
0 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-23 16:24 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Yoshinori Sato, David Hildenbrand, Weiwei Li,
Richard Henderson, Michael Rolnik, Ilya Leoshkevich,
Peter Maydell, qemu-ppc, Paolo Bonzini, qemu-riscv, Cleber Rosa,
Thomas Huth, Song Gao, qemu-arm, Pierrick Bouvier, John Snow,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
Alex Bennée <alex.bennee@linaro.org> writes:
> Akihiko Odaki <akihiko.odaki@daynix.com> writes:
<snip>
>>> What about if I just key based of gdb_regnum and we accept that that
>>> might break the one heterogeneous system we model today?
>>>
>>
>> That's the best option in my opinion. gdbstub won't work well with
>> such a system anyway, and fixing it will need something similar to
>> GHashTable. But if I would fix gdbstub for a heterogeneous system, I
>> would add a field to CPUClass instead of having a GHashTable keyed
>> with tuples of CPUClass pointers and register numbers. It should be
>> fine considering that CPUState already has gdbstub-specific fields
>> like gdb_regs.
>
> It would be nice to move all register code into CPUClass to avoid
> repeating ourselves but I suspect that is quite an invasive change for a
> later series. Currently all the CPUClass values are set on init and
> shouldn't really be changed after that otherwise we'll have to start
> messing with locking.
Peter pointed out we can see different register sets for the same
CPUClass but with different features enabled which kills that idea. I've
just sent v2 which re-factors the plugin data a little and stores a per
CPUPluginState hash table.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 19/23] contrib/plugins: fix imatch
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (17 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 18/23] plugins: add an API to read registers Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 20/23] contrib/plugins: extend execlog to track register changes Alex Bennée
` (3 subsequent siblings)
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
We can't directly save the ephemeral imatch from argv as that memory
will get recycled.
Message-Id: <20240103173349.398526-40-alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
contrib/plugins/execlog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c
index 82dc2f584e2..f262e5555eb 100644
--- a/contrib/plugins/execlog.c
+++ b/contrib/plugins/execlog.c
@@ -199,7 +199,7 @@ static void parse_insn_match(char *match)
if (!imatches) {
imatches = g_ptr_array_new();
}
- g_ptr_array_add(imatches, match);
+ g_ptr_array_add(imatches, g_strdup(match));
}
static void parse_vaddr_match(char *match)
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 20/23] contrib/plugins: extend execlog to track register changes
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (18 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 19/23] contrib/plugins: fix imatch Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-17 11:36 ` Pierrick Bouvier
2024-02-16 16:30 ` [PATCH 21/23] docs/devel: lift example and plugin API sections up Alex Bennée
` (2 subsequent siblings)
22 siblings, 1 reply; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested in tracking.
Example usage:
./qemu-aarch64 -D plugin.log -d plugin \
-cpu max,sve256=on \
-plugin contrib/plugins/libexeclog.so,reg=sp,reg=z\* \
./tests/tcg/aarch64-linux-user/sha512-sve
will display in the execlog any changes to the stack pointer (sp) and
the SVE Z registers.
As testing registers every instruction will be quite a heavy operation
there is an additional flag which attempts to optimise the register
tracking by only instrumenting instructions which are likely to change
its value. This relies on the QEMU disassembler showing up the register
names in disassembly so is an explicit opt-in.
Message-Id: <20240103173349.398526-41-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Based-On: <20231025093128.33116-19-akihiko.odaki@daynix.com>
---
v3
- just use a GArray for the CPU array
- drop duplicate of cpu_index
v4
- rebase and api fixups
- I accidentally squashed the optimisation last round so update
commit message with the details.
---
docs/devel/tcg-plugins.rst | 17 +-
contrib/plugins/execlog.c | 316 +++++++++++++++++++++++++++++++------
2 files changed, 281 insertions(+), 52 deletions(-)
diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst
index 81dcd43a612..fa7421279f5 100644
--- a/docs/devel/tcg-plugins.rst
+++ b/docs/devel/tcg-plugins.rst
@@ -497,6 +497,22 @@ arguments if required::
$ qemu-system-arm $(QEMU_ARGS) \
-plugin ./contrib/plugins/libexeclog.so,ifilter=st1w,afilter=0x40001808 -d plugin
+This plugin can also dump registers when they change value. Specify the name of the
+registers with multiple ``reg`` options. You can also use glob style matching if you wish::
+
+ $ qemu-system-arm $(QEMU_ARGS) \
+ -plugin ./contrib/plugins/libexeclog.so,reg=\*_el2,reg=sp -d plugin
+
+Be aware that each additional register to check will slow down
+execution quite considerably. You can optimise the number of register
+checks done by using the rdisas option. This will only instrument
+instructions that mention the registers in question in disassembly.
+This is not foolproof as some instructions implicitly change
+instructions. You can use the ifilter to catch these cases:
+
+ $ qemu-system-arm $(QEMU_ARGS) \
+ -plugin ./contrib/plugins/libexeclog.so,ifilter=msr,ifilter=blr,reg=x30,reg=\*_el1,rdisas=on
+
- contrib/plugins/cache.c
Cache modelling plugin that measures the performance of a given L1 cache
@@ -583,4 +599,3 @@ The following API is generated from the inline documentation in
include the full kernel-doc annotations.
.. kernel-doc:: include/qemu/qemu-plugin.h
-
diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c
index f262e5555eb..dd7168cb548 100644
--- a/contrib/plugins/execlog.c
+++ b/contrib/plugins/execlog.c
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2021, Alexandre Iooss <erdnaxe@crans.org>
*
- * Log instruction execution with memory access.
+ * Log instruction execution with memory access and register changes
*
* License: GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -15,29 +15,40 @@
#include <qemu-plugin.h>
+typedef struct {
+ struct qemu_plugin_register *handle;
+ GByteArray *last;
+ GByteArray *new;
+ const char *name;
+} Register;
+
+typedef struct CPU {
+ /* Store last executed instruction on each vCPU as a GString */
+ GString *last_exec;
+ /* Ptr array of Register */
+ GPtrArray *registers;
+} CPU;
+
QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION;
-/* Store last executed instruction on each vCPU as a GString */
-static GPtrArray *last_exec;
+static GArray *cpus;
static GRWLock expand_array_lock;
static GPtrArray *imatches;
static GArray *amatches;
+static GPtrArray *rmatches;
+static bool disas_assist;
+static GMutex add_reg_name_lock;
+static GPtrArray *all_reg_names;
-/*
- * Expand last_exec array.
- *
- * As we could have multiple threads trying to do this we need to
- * serialise the expansion under a lock.
- */
-static void expand_last_exec(int cpu_index)
+static CPU *get_cpu(int vcpu_index)
{
- g_rw_lock_writer_lock(&expand_array_lock);
- while (cpu_index >= last_exec->len) {
- GString *s = g_string_new(NULL);
- g_ptr_array_add(last_exec, s);
- }
- g_rw_lock_writer_unlock(&expand_array_lock);
+ CPU *c;
+ g_rw_lock_reader_lock(&expand_array_lock);
+ c = &g_array_index(cpus, CPU, vcpu_index);
+ g_rw_lock_reader_unlock(&expand_array_lock);
+
+ return c;
}
/**
@@ -46,13 +57,10 @@ static void expand_last_exec(int cpu_index)
static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info,
uint64_t vaddr, void *udata)
{
- GString *s;
+ CPU *c = get_cpu(cpu_index);
+ GString *s = c->last_exec;
/* Find vCPU in array */
- g_rw_lock_reader_lock(&expand_array_lock);
- g_assert(cpu_index < last_exec->len);
- s = g_ptr_array_index(last_exec, cpu_index);
- g_rw_lock_reader_unlock(&expand_array_lock);
/* Indicate type of memory access */
if (qemu_plugin_mem_is_store(info)) {
@@ -73,32 +81,91 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info,
}
/**
- * Log instruction execution
+ * Log instruction execution, outputting the last one.
+ *
+ * vcpu_insn_exec() is a copy and paste of vcpu_insn_exec_with_regs()
+ * without the checking of register values when we've attempted to
+ * optimise with disas_assist.
*/
-static void vcpu_insn_exec(unsigned int cpu_index, void *udata)
+static void insn_check_regs(CPU *cpu)
{
- GString *s;
+ for (int n = 0; n < cpu->registers->len; n++) {
+ Register *reg = cpu->registers->pdata[n];
+ int sz;
- /* Find or create vCPU in array */
- g_rw_lock_reader_lock(&expand_array_lock);
- if (cpu_index >= last_exec->len) {
- g_rw_lock_reader_unlock(&expand_array_lock);
- expand_last_exec(cpu_index);
- g_rw_lock_reader_lock(&expand_array_lock);
+ g_byte_array_set_size(reg->new, 0);
+ sz = qemu_plugin_read_register(reg->handle, reg->new);
+ g_assert(sz == reg->last->len);
+
+ if (memcmp(reg->last->data, reg->new->data, sz)) {
+ GByteArray *temp = reg->last;
+ g_string_append_printf(cpu->last_exec, ", %s -> 0x", reg->name);
+ /* TODO: handle BE properly */
+ for (int i = sz; i >= 0; i--) {
+ g_string_append_printf(cpu->last_exec, "%02x",
+ reg->new->data[i]);
+ }
+ reg->last = reg->new;
+ reg->new = temp;
+ }
+ }
+}
+
+/* Log last instruction while checking registers */
+static void vcpu_insn_exec_with_regs(unsigned int cpu_index, void *udata)
+{
+ CPU *cpu = get_cpu(cpu_index);
+
+ /* Print previous instruction in cache */
+ if (cpu->last_exec->len) {
+ if (cpu->registers) {
+ insn_check_regs(cpu);
+ }
+
+ qemu_plugin_outs(cpu->last_exec->str);
+ qemu_plugin_outs("\n");
+ }
+
+ /* Store new instruction in cache */
+ /* vcpu_mem will add memory access information to last_exec */
+ g_string_printf(cpu->last_exec, "%u, ", cpu_index);
+ g_string_append(cpu->last_exec, (char *)udata);
+}
+
+/* Log last instruction while checking registers, ignore next */
+static void vcpu_insn_exec_only_regs(unsigned int cpu_index, void *udata)
+{
+ CPU *cpu = get_cpu(cpu_index);
+
+ /* Print previous instruction in cache */
+ if (cpu->last_exec->len) {
+ if (cpu->registers) {
+ insn_check_regs(cpu);
+ }
+
+ qemu_plugin_outs(cpu->last_exec->str);
+ qemu_plugin_outs("\n");
}
- s = g_ptr_array_index(last_exec, cpu_index);
- g_rw_lock_reader_unlock(&expand_array_lock);
+
+ /* reset */
+ cpu->last_exec->len = 0;
+}
+
+/* Log last instruction without checking regs, setup next */
+static void vcpu_insn_exec(unsigned int cpu_index, void *udata)
+{
+ CPU *cpu = get_cpu(cpu_index);
/* Print previous instruction in cache */
- if (s->len) {
- qemu_plugin_outs(s->str);
+ if (cpu->last_exec->len) {
+ qemu_plugin_outs(cpu->last_exec->str);
qemu_plugin_outs("\n");
}
/* Store new instruction in cache */
/* vcpu_mem will add memory access information to last_exec */
- g_string_printf(s, "%u, ", cpu_index);
- g_string_append(s, (char *)udata);
+ g_string_printf(cpu->last_exec, "%u, ", cpu_index);
+ g_string_append(cpu->last_exec, (char *)udata);
}
/**
@@ -111,6 +178,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
{
struct qemu_plugin_insn *insn;
bool skip = (imatches || amatches);
+ bool check_regs_this = rmatches;
+ bool check_regs_next = false;
size_t n = qemu_plugin_tb_n_insns(tb);
for (size_t i = 0; i < n; i++) {
@@ -131,7 +200,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
/*
* If we are filtering we better check out if we have any
* hits. The skip "latches" so we can track memory accesses
- * after the instruction we care about.
+ * after the instruction we care about. Also enable register
+ * checking on the next instruction.
*/
if (skip && imatches) {
int j;
@@ -139,6 +209,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
char *m = g_ptr_array_index(imatches, j);
if (g_str_has_prefix(insn_disas, m)) {
skip = false;
+ check_regs_next = rmatches;
}
}
}
@@ -153,8 +224,39 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
}
}
+ /*
+ * Check the disassembly to see if a register we care about
+ * will be affected by this instruction. This relies on the
+ * dissembler doing something sensible for the registers we
+ * care about.
+ */
+ if (disas_assist && rmatches) {
+ check_regs_next = false;
+ gchar *args = g_strstr_len(insn_disas, -1, " ");
+ for (int n = 0; n < all_reg_names->len; n++) {
+ gchar *reg = g_ptr_array_index(all_reg_names, n);
+ if (g_strrstr(args, reg)) {
+ check_regs_next = true;
+ skip = false;
+ }
+ }
+ }
+
+ /*
+ * We now have 3 choices:
+ *
+ * - Log insn
+ * - Log insn while checking registers
+ * - Don't log this insn but check if last insn changed registers
+ */
+
if (skip) {
- g_free(insn_disas);
+ if (check_regs_this) {
+ qemu_plugin_register_vcpu_insn_exec_cb(insn,
+ vcpu_insn_exec_only_regs,
+ QEMU_PLUGIN_CB_R_REGS,
+ NULL);
+ }
} else {
uint32_t insn_opcode;
insn_opcode = *((uint32_t *)qemu_plugin_insn_data(insn));
@@ -167,30 +269,124 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
QEMU_PLUGIN_MEM_RW, NULL);
/* Register callback on instruction */
- qemu_plugin_register_vcpu_insn_exec_cb(insn, vcpu_insn_exec,
- QEMU_PLUGIN_CB_NO_REGS, output);
+ if (check_regs_this) {
+ qemu_plugin_register_vcpu_insn_exec_cb(
+ insn, vcpu_insn_exec_with_regs,
+ QEMU_PLUGIN_CB_R_REGS,
+ output);
+ } else {
+ qemu_plugin_register_vcpu_insn_exec_cb(
+ insn, vcpu_insn_exec,
+ QEMU_PLUGIN_CB_NO_REGS,
+ output);
+ }
/* reset skip */
skip = (imatches || amatches);
}
+ /* set regs for next */
+ if (disas_assist && rmatches) {
+ check_regs_this = check_regs_next;
+ }
+
+ g_free(insn_disas);
}
}
+static Register *init_vcpu_register(qemu_plugin_reg_descriptor *desc)
+{
+ Register *reg = g_new0(Register, 1);
+ g_autofree gchar *lower = g_utf8_strdown(desc->name, -1);
+ int r;
+
+ reg->handle = desc->handle;
+ reg->name = g_intern_string(lower);
+ reg->last = g_byte_array_new();
+ reg->new = g_byte_array_new();
+
+ /* read the initial value */
+ r = qemu_plugin_read_register(reg->handle, reg->last);
+ g_assert(r > 0);
+ return reg;
+}
+
+static GPtrArray *registers_init(int vcpu_index)
+{
+ g_autoptr(GPtrArray) registers = g_ptr_array_new();
+ g_autoptr(GArray) reg_list = qemu_plugin_get_registers();
+
+ if (rmatches && reg_list && reg_list->len) {
+ /*
+ * Go through each register in the complete list and
+ * see if we want to track it.
+ */
+ for (int r = 0; r < reg_list->len; r++) {
+ qemu_plugin_reg_descriptor *rd = &g_array_index(
+ reg_list, qemu_plugin_reg_descriptor, r);
+ for (int p = 0; p < rmatches->len; p++) {
+ g_autoptr(GPatternSpec) pat = g_pattern_spec_new(rmatches->pdata[p]);
+ g_autofree gchar *rd_lower = g_utf8_strdown(rd->name, -1);
+ if (g_pattern_match_string(pat, rd->name) ||
+ g_pattern_match_string(pat, rd_lower)) {
+ Register *reg = init_vcpu_register(rd);
+ g_ptr_array_add(registers, reg);
+
+ /* we need a list of regnames at TB translation time */
+ if (disas_assist) {
+ g_mutex_lock(&add_reg_name_lock);
+ if (!g_ptr_array_find(all_reg_names, reg->name, NULL)) {
+ g_ptr_array_add(all_reg_names, reg->name);
+ }
+ g_mutex_unlock(&add_reg_name_lock);
+ }
+ }
+ }
+ }
+ }
+
+ return registers->len ? g_steal_pointer(®isters) : NULL;
+}
+
+/*
+ * Initialise a new vcpu/thread with:
+ * - last_exec tracking data
+ * - list of tracked registers
+ * - initial value of registers
+ *
+ * As we could have multiple threads trying to do this we need to
+ * serialise the expansion under a lock.
+ */
+static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index)
+{
+ CPU *c;
+
+ g_rw_lock_writer_lock(&expand_array_lock);
+ if (vcpu_index >= cpus->len) {
+ g_array_set_size(cpus, vcpu_index + 1);
+ }
+ g_rw_lock_writer_unlock(&expand_array_lock);
+
+ c = get_cpu(vcpu_index);
+ c->last_exec = g_string_new(NULL);
+ c->registers = registers_init(vcpu_index);
+}
+
/**
* On plugin exit, print last instruction in cache
*/
static void plugin_exit(qemu_plugin_id_t id, void *p)
{
guint i;
- GString *s;
- for (i = 0; i < last_exec->len; i++) {
- s = g_ptr_array_index(last_exec, i);
- if (s->str) {
- qemu_plugin_outs(s->str);
+ g_rw_lock_reader_lock(&expand_array_lock);
+ for (i = 0; i < cpus->len; i++) {
+ CPU *c = get_cpu(i);
+ if (c->last_exec && c->last_exec->str) {
+ qemu_plugin_outs(c->last_exec->str);
qemu_plugin_outs("\n");
}
}
+ g_rw_lock_reader_unlock(&expand_array_lock);
}
/* Add a match to the array of matches */
@@ -212,6 +408,18 @@ static void parse_vaddr_match(char *match)
g_array_append_val(amatches, v);
}
+/*
+ * We have to wait until vCPUs are started before we can check the
+ * patterns find anything.
+ */
+static void add_regpat(char *regpat)
+{
+ if (!rmatches) {
+ rmatches = g_ptr_array_new();
+ }
+ g_ptr_array_add(rmatches, g_strdup(regpat));
+}
+
/**
* Install the plugin
*/
@@ -223,11 +431,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
* Initialize dynamic array to cache vCPU instruction. In user mode
* we don't know the size before emulation.
*/
- if (info->system_emulation) {
- last_exec = g_ptr_array_sized_new(info->system.max_vcpus);
- } else {
- last_exec = g_ptr_array_new();
- }
+ cpus = g_array_sized_new(true, true, sizeof(CPU),
+ info->system_emulation ? info->system.max_vcpus : 1);
for (int i = 0; i < argc; i++) {
char *opt = argv[i];
@@ -236,13 +441,22 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
parse_insn_match(tokens[1]);
} else if (g_strcmp0(tokens[0], "afilter") == 0) {
parse_vaddr_match(tokens[1]);
+ } else if (g_strcmp0(tokens[0], "reg") == 0) {
+ add_regpat(tokens[1]);
+ } else if (g_strcmp0(tokens[0], "rdisas") == 0) {
+ if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &disas_assist)) {
+ fprintf(stderr, "boolean argument parsing failed: %s\n", opt);
+ return -1;
+ }
+ all_reg_names = g_ptr_array_new();
} else {
fprintf(stderr, "option parsing failed: %s\n", opt);
return -1;
}
}
- /* Register translation block and exit callbacks */
+ /* Register init, translation block and exit callbacks */
+ qemu_plugin_register_vcpu_init_cb(id, vcpu_init);
qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [PATCH 20/23] contrib/plugins: extend execlog to track register changes
2024-02-16 16:30 ` [PATCH 20/23] contrib/plugins: extend execlog to track register changes Alex Bennée
@ 2024-02-17 11:36 ` Pierrick Bouvier
0 siblings, 0 replies; 38+ messages in thread
From: Pierrick Bouvier @ 2024-02-17 11:36 UTC (permalink / raw)
To: Alex Bennée, qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, John Snow, Cédric Le Goater, Nicholas Piggin,
qemu-s390x, Laurent Vivier, Edgar E. Iglesias,
Daniel Henrique Barboza, Yanan Wang, Palmer Dabbelt,
Marcel Apfelbaum, Brian Cain, Mahmoud Mandour, Alexandre Iooss,
Bin Meng, Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei, Akihiko Odaki
On 2/16/24 20:30, Alex Bennée wrote:
> With the new plugin register API we can now track changes to register
> values. Currently the implementation is fairly dumb which will slow
> down if a large number of register values are being tracked. This
> could be improved by only instrumenting instructions which mention
> registers we are interested in tracking.
>
> Example usage:
>
> ./qemu-aarch64 -D plugin.log -d plugin \
> -cpu max,sve256=on \
> -plugin contrib/plugins/libexeclog.so,reg=sp,reg=z\* \
> ./tests/tcg/aarch64-linux-user/sha512-sve
>
> will display in the execlog any changes to the stack pointer (sp) and
> the SVE Z registers.
>
> As testing registers every instruction will be quite a heavy operation
> there is an additional flag which attempts to optimise the register
> tracking by only instrumenting instructions which are likely to change
> its value. This relies on the QEMU disassembler showing up the register
> names in disassembly so is an explicit opt-in.
>
> Message-Id: <20240103173349.398526-41-alex.bennee@linaro.org>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
> Based-On: <20231025093128.33116-19-akihiko.odaki@daynix.com>
>
> ---
> v3
> - just use a GArray for the CPU array
> - drop duplicate of cpu_index
> v4
> - rebase and api fixups
> - I accidentally squashed the optimisation last round so update
> commit message with the details.
> ---
> docs/devel/tcg-plugins.rst | 17 +-
> contrib/plugins/execlog.c | 316 +++++++++++++++++++++++++++++++------
> 2 files changed, 281 insertions(+), 52 deletions(-)
>
> diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst
> index 81dcd43a612..fa7421279f5 100644
> --- a/docs/devel/tcg-plugins.rst
> +++ b/docs/devel/tcg-plugins.rst
> @@ -497,6 +497,22 @@ arguments if required::
> $ qemu-system-arm $(QEMU_ARGS) \
> -plugin ./contrib/plugins/libexeclog.so,ifilter=st1w,afilter=0x40001808 -d plugin
>
> +This plugin can also dump registers when they change value. Specify the name of the
> +registers with multiple ``reg`` options. You can also use glob style matching if you wish::
> +
> + $ qemu-system-arm $(QEMU_ARGS) \
> + -plugin ./contrib/plugins/libexeclog.so,reg=\*_el2,reg=sp -d plugin
> +
> +Be aware that each additional register to check will slow down
> +execution quite considerably. You can optimise the number of register
> +checks done by using the rdisas option. This will only instrument
> +instructions that mention the registers in question in disassembly.
> +This is not foolproof as some instructions implicitly change
> +instructions. You can use the ifilter to catch these cases:
> +
> + $ qemu-system-arm $(QEMU_ARGS) \
> + -plugin ./contrib/plugins/libexeclog.so,ifilter=msr,ifilter=blr,reg=x30,reg=\*_el1,rdisas=on
> +
> - contrib/plugins/cache.c
>
> Cache modelling plugin that measures the performance of a given L1 cache
> @@ -583,4 +599,3 @@ The following API is generated from the inline documentation in
> include the full kernel-doc annotations.
>
> .. kernel-doc:: include/qemu/qemu-plugin.h
> -
> diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c
> index f262e5555eb..dd7168cb548 100644
> --- a/contrib/plugins/execlog.c
> +++ b/contrib/plugins/execlog.c
> @@ -1,7 +1,7 @@
> /*
> * Copyright (C) 2021, Alexandre Iooss <erdnaxe@crans.org>
> *
> - * Log instruction execution with memory access.
> + * Log instruction execution with memory access and register changes
> *
> * License: GNU GPL, version 2 or later.
> * See the COPYING file in the top-level directory.
> @@ -15,29 +15,40 @@
>
> #include <qemu-plugin.h>
>
> +typedef struct {
> + struct qemu_plugin_register *handle;
> + GByteArray *last;
> + GByteArray *new;
> + const char *name;
> +} Register;
> +
> +typedef struct CPU {
> + /* Store last executed instruction on each vCPU as a GString */
> + GString *last_exec;
> + /* Ptr array of Register */
> + GPtrArray *registers;
> +} CPU;
> +
> QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION;
>
> -/* Store last executed instruction on each vCPU as a GString */
> -static GPtrArray *last_exec;
> +static GArray *cpus;
> static GRWLock expand_array_lock;
>
> static GPtrArray *imatches;
> static GArray *amatches;
> +static GPtrArray *rmatches;
> +static bool disas_assist;
> +static GMutex add_reg_name_lock;
> +static GPtrArray *all_reg_names;
>
> -/*
> - * Expand last_exec array.
> - *
> - * As we could have multiple threads trying to do this we need to
> - * serialise the expansion under a lock.
> - */
> -static void expand_last_exec(int cpu_index)
> +static CPU *get_cpu(int vcpu_index)
> {
> - g_rw_lock_writer_lock(&expand_array_lock);
> - while (cpu_index >= last_exec->len) {
> - GString *s = g_string_new(NULL);
> - g_ptr_array_add(last_exec, s);
> - }
> - g_rw_lock_writer_unlock(&expand_array_lock);
> + CPU *c;
> + g_rw_lock_reader_lock(&expand_array_lock);
> + c = &g_array_index(cpus, CPU, vcpu_index);
> + g_rw_lock_reader_unlock(&expand_array_lock);
> +
> + return c;
> }
>
> /**
> @@ -46,13 +57,10 @@ static void expand_last_exec(int cpu_index)
> static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info,
> uint64_t vaddr, void *udata)
> {
> - GString *s;
> + CPU *c = get_cpu(cpu_index);
> + GString *s = c->last_exec;
>
> /* Find vCPU in array */
> - g_rw_lock_reader_lock(&expand_array_lock);
> - g_assert(cpu_index < last_exec->len);
> - s = g_ptr_array_index(last_exec, cpu_index);
> - g_rw_lock_reader_unlock(&expand_array_lock);
>
> /* Indicate type of memory access */
> if (qemu_plugin_mem_is_store(info)) {
> @@ -73,32 +81,91 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info,
> }
>
> /**
> - * Log instruction execution
> + * Log instruction execution, outputting the last one.
> + *
> + * vcpu_insn_exec() is a copy and paste of vcpu_insn_exec_with_regs()
> + * without the checking of register values when we've attempted to
> + * optimise with disas_assist.
> */
> -static void vcpu_insn_exec(unsigned int cpu_index, void *udata)
> +static void insn_check_regs(CPU *cpu)
> {
> - GString *s;
> + for (int n = 0; n < cpu->registers->len; n++) {
> + Register *reg = cpu->registers->pdata[n];
> + int sz;
>
> - /* Find or create vCPU in array */
> - g_rw_lock_reader_lock(&expand_array_lock);
> - if (cpu_index >= last_exec->len) {
> - g_rw_lock_reader_unlock(&expand_array_lock);
> - expand_last_exec(cpu_index);
> - g_rw_lock_reader_lock(&expand_array_lock);
> + g_byte_array_set_size(reg->new, 0);
> + sz = qemu_plugin_read_register(reg->handle, reg->new);
> + g_assert(sz == reg->last->len);
> +
> + if (memcmp(reg->last->data, reg->new->data, sz)) {
> + GByteArray *temp = reg->last;
> + g_string_append_printf(cpu->last_exec, ", %s -> 0x", reg->name);
> + /* TODO: handle BE properly */
> + for (int i = sz; i >= 0; i--) {
> + g_string_append_printf(cpu->last_exec, "%02x",
> + reg->new->data[i]);
> + }
> + reg->last = reg->new;
> + reg->new = temp;
> + }
> + }
> +}
> +
> +/* Log last instruction while checking registers */
> +static void vcpu_insn_exec_with_regs(unsigned int cpu_index, void *udata)
> +{
> + CPU *cpu = get_cpu(cpu_index);
> +
> + /* Print previous instruction in cache */
> + if (cpu->last_exec->len) {
> + if (cpu->registers) {
> + insn_check_regs(cpu);
> + }
> +
> + qemu_plugin_outs(cpu->last_exec->str);
> + qemu_plugin_outs("\n");
> + }
> +
> + /* Store new instruction in cache */
> + /* vcpu_mem will add memory access information to last_exec */
> + g_string_printf(cpu->last_exec, "%u, ", cpu_index);
> + g_string_append(cpu->last_exec, (char *)udata);
> +}
> +
> +/* Log last instruction while checking registers, ignore next */
> +static void vcpu_insn_exec_only_regs(unsigned int cpu_index, void *udata)
> +{
> + CPU *cpu = get_cpu(cpu_index);
> +
> + /* Print previous instruction in cache */
> + if (cpu->last_exec->len) {
> + if (cpu->registers) {
> + insn_check_regs(cpu);
> + }
> +
> + qemu_plugin_outs(cpu->last_exec->str);
> + qemu_plugin_outs("\n");
> }
> - s = g_ptr_array_index(last_exec, cpu_index);
> - g_rw_lock_reader_unlock(&expand_array_lock);
> +
> + /* reset */
> + cpu->last_exec->len = 0;
> +}
> +
> +/* Log last instruction without checking regs, setup next */
> +static void vcpu_insn_exec(unsigned int cpu_index, void *udata)
> +{
> + CPU *cpu = get_cpu(cpu_index);
>
> /* Print previous instruction in cache */
> - if (s->len) {
> - qemu_plugin_outs(s->str);
> + if (cpu->last_exec->len) {
> + qemu_plugin_outs(cpu->last_exec->str);
> qemu_plugin_outs("\n");
> }
>
> /* Store new instruction in cache */
> /* vcpu_mem will add memory access information to last_exec */
> - g_string_printf(s, "%u, ", cpu_index);
> - g_string_append(s, (char *)udata);
> + g_string_printf(cpu->last_exec, "%u, ", cpu_index);
> + g_string_append(cpu->last_exec, (char *)udata);
> }
>
> /**
> @@ -111,6 +178,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
> {
> struct qemu_plugin_insn *insn;
> bool skip = (imatches || amatches);
> + bool check_regs_this = rmatches;
> + bool check_regs_next = false;
>
> size_t n = qemu_plugin_tb_n_insns(tb);
> for (size_t i = 0; i < n; i++) {
> @@ -131,7 +200,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
> /*
> * If we are filtering we better check out if we have any
> * hits. The skip "latches" so we can track memory accesses
> - * after the instruction we care about.
> + * after the instruction we care about. Also enable register
> + * checking on the next instruction.
> */
> if (skip && imatches) {
> int j;
> @@ -139,6 +209,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
> char *m = g_ptr_array_index(imatches, j);
> if (g_str_has_prefix(insn_disas, m)) {
> skip = false;
> + check_regs_next = rmatches;
> }
> }
> }
> @@ -153,8 +224,39 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
> }
> }
>
> + /*
> + * Check the disassembly to see if a register we care about
> + * will be affected by this instruction. This relies on the
> + * dissembler doing something sensible for the registers we
> + * care about.
> + */
> + if (disas_assist && rmatches) {
> + check_regs_next = false;
> + gchar *args = g_strstr_len(insn_disas, -1, " ");
> + for (int n = 0; n < all_reg_names->len; n++) {
> + gchar *reg = g_ptr_array_index(all_reg_names, n);
> + if (g_strrstr(args, reg)) {
> + check_regs_next = true;
> + skip = false;
> + }
> + }
> + }
> +
> + /*
> + * We now have 3 choices:
> + *
> + * - Log insn
> + * - Log insn while checking registers
> + * - Don't log this insn but check if last insn changed registers
> + */
> +
> if (skip) {
> - g_free(insn_disas);
> + if (check_regs_this) {
> + qemu_plugin_register_vcpu_insn_exec_cb(insn,
> + vcpu_insn_exec_only_regs,
> + QEMU_PLUGIN_CB_R_REGS,
> + NULL);
> + }
> } else {
> uint32_t insn_opcode;
> insn_opcode = *((uint32_t *)qemu_plugin_insn_data(insn));
> @@ -167,30 +269,124 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
> QEMU_PLUGIN_MEM_RW, NULL);
>
> /* Register callback on instruction */
> - qemu_plugin_register_vcpu_insn_exec_cb(insn, vcpu_insn_exec,
> - QEMU_PLUGIN_CB_NO_REGS, output);
> + if (check_regs_this) {
> + qemu_plugin_register_vcpu_insn_exec_cb(
> + insn, vcpu_insn_exec_with_regs,
> + QEMU_PLUGIN_CB_R_REGS,
> + output);
> + } else {
> + qemu_plugin_register_vcpu_insn_exec_cb(
> + insn, vcpu_insn_exec,
> + QEMU_PLUGIN_CB_NO_REGS,
> + output);
> + }
>
> /* reset skip */
> skip = (imatches || amatches);
> }
>
> + /* set regs for next */
> + if (disas_assist && rmatches) {
> + check_regs_this = check_regs_next;
> + }
> +
> + g_free(insn_disas);
> }
> }
>
> +static Register *init_vcpu_register(qemu_plugin_reg_descriptor *desc)
> +{
> + Register *reg = g_new0(Register, 1);
> + g_autofree gchar *lower = g_utf8_strdown(desc->name, -1);
> + int r;
> +
> + reg->handle = desc->handle;
> + reg->name = g_intern_string(lower);
> + reg->last = g_byte_array_new();
> + reg->new = g_byte_array_new();
> +
> + /* read the initial value */
> + r = qemu_plugin_read_register(reg->handle, reg->last);
> + g_assert(r > 0);
> + return reg;
> +}
> +
> +static GPtrArray *registers_init(int vcpu_index)
> +{
> + g_autoptr(GPtrArray) registers = g_ptr_array_new();
> + g_autoptr(GArray) reg_list = qemu_plugin_get_registers();
> +
> + if (rmatches && reg_list && reg_list->len) {
> + /*
> + * Go through each register in the complete list and
> + * see if we want to track it.
> + */
> + for (int r = 0; r < reg_list->len; r++) {
> + qemu_plugin_reg_descriptor *rd = &g_array_index(
> + reg_list, qemu_plugin_reg_descriptor, r);
> + for (int p = 0; p < rmatches->len; p++) {
> + g_autoptr(GPatternSpec) pat = g_pattern_spec_new(rmatches->pdata[p]);
> + g_autofree gchar *rd_lower = g_utf8_strdown(rd->name, -1);
> + if (g_pattern_match_string(pat, rd->name) ||
> + g_pattern_match_string(pat, rd_lower)) {
> + Register *reg = init_vcpu_register(rd);
> + g_ptr_array_add(registers, reg);
> +
> + /* we need a list of regnames at TB translation time */
> + if (disas_assist) {
> + g_mutex_lock(&add_reg_name_lock);
> + if (!g_ptr_array_find(all_reg_names, reg->name, NULL)) {
> + g_ptr_array_add(all_reg_names, reg->name);
> + }
> + g_mutex_unlock(&add_reg_name_lock);
> + }
> + }
> + }
> + }
> + }
> +
> + return registers->len ? g_steal_pointer(®isters) : NULL;
> +}
> +
> +/*
> + * Initialise a new vcpu/thread with:
> + * - last_exec tracking data
> + * - list of tracked registers
> + * - initial value of registers
> + *
> + * As we could have multiple threads trying to do this we need to
> + * serialise the expansion under a lock.
> + */
> +static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index)
> +{
> + CPU *c;
> +
> + g_rw_lock_writer_lock(&expand_array_lock);
> + if (vcpu_index >= cpus->len) {
> + g_array_set_size(cpus, vcpu_index + 1);
> + }
> + g_rw_lock_writer_unlock(&expand_array_lock);
> +
> + c = get_cpu(vcpu_index);
> + c->last_exec = g_string_new(NULL);
> + c->registers = registers_init(vcpu_index);
> +}
> +
> /**
> * On plugin exit, print last instruction in cache
> */
> static void plugin_exit(qemu_plugin_id_t id, void *p)
> {
> guint i;
> - GString *s;
> - for (i = 0; i < last_exec->len; i++) {
> - s = g_ptr_array_index(last_exec, i);
> - if (s->str) {
> - qemu_plugin_outs(s->str);
> + g_rw_lock_reader_lock(&expand_array_lock);
> + for (i = 0; i < cpus->len; i++) {
> + CPU *c = get_cpu(i);
> + if (c->last_exec && c->last_exec->str) {
> + qemu_plugin_outs(c->last_exec->str);
> qemu_plugin_outs("\n");
> }
> }
> + g_rw_lock_reader_unlock(&expand_array_lock);
> }
>
> /* Add a match to the array of matches */
> @@ -212,6 +408,18 @@ static void parse_vaddr_match(char *match)
> g_array_append_val(amatches, v);
> }
>
> +/*
> + * We have to wait until vCPUs are started before we can check the
> + * patterns find anything.
> + */
> +static void add_regpat(char *regpat)
> +{
> + if (!rmatches) {
> + rmatches = g_ptr_array_new();
> + }
> + g_ptr_array_add(rmatches, g_strdup(regpat));
> +}
> +
> /**
> * Install the plugin
> */
> @@ -223,11 +431,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
> * Initialize dynamic array to cache vCPU instruction. In user mode
> * we don't know the size before emulation.
> */
> - if (info->system_emulation) {
> - last_exec = g_ptr_array_sized_new(info->system.max_vcpus);
> - } else {
> - last_exec = g_ptr_array_new();
> - }
> + cpus = g_array_sized_new(true, true, sizeof(CPU),
> + info->system_emulation ? info->system.max_vcpus : 1);
>
> for (int i = 0; i < argc; i++) {
> char *opt = argv[i];
> @@ -236,13 +441,22 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
> parse_insn_match(tokens[1]);
> } else if (g_strcmp0(tokens[0], "afilter") == 0) {
> parse_vaddr_match(tokens[1]);
> + } else if (g_strcmp0(tokens[0], "reg") == 0) {
> + add_regpat(tokens[1]);
> + } else if (g_strcmp0(tokens[0], "rdisas") == 0) {
> + if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &disas_assist)) {
> + fprintf(stderr, "boolean argument parsing failed: %s\n", opt);
> + return -1;
> + }
> + all_reg_names = g_ptr_array_new();
> } else {
> fprintf(stderr, "option parsing failed: %s\n", opt);
> return -1;
> }
> }
>
> - /* Register translation block and exit callbacks */
> + /* Register init, translation block and exit callbacks */
> + qemu_plugin_register_vcpu_init_cb(id, vcpu_init);
> qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
> qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 21/23] docs/devel: lift example and plugin API sections up
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (19 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 20/23] contrib/plugins: extend execlog to track register changes Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 22/23] docs/devel: document some plugin assumptions Alex Bennée
2024-02-16 16:30 ` [PATCH 23/23] docs/devel: plugins can trigger a tb flush Alex Bennée
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
This makes them a bit more visible in the TCG emulation menu rather
than hiding them away bellow the ToC limit.
Message-Id: <20240103173349.398526-43-alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
docs/devel/tcg-plugins.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst
index fa7421279f5..535a74684c5 100644
--- a/docs/devel/tcg-plugins.rst
+++ b/docs/devel/tcg-plugins.rst
@@ -143,7 +143,7 @@ requested. The plugin isn't completely uninstalled until the safe work
has executed while all vCPUs are quiescent.
Example Plugins
----------------
+===============
There are a number of plugins included with QEMU and you are
encouraged to contribute your own plugins plugins upstream. There is a
@@ -591,8 +591,8 @@ The plugin has a number of arguments, all of them are optional:
configuration arguments implies ``l2=on``.
(default: N = 2097152 (2MB), B = 64, A = 16)
-API
----
+Plugin API
+==========
The following API is generated from the inline documentation in
``include/qemu/qemu-plugin.h``. Please ensure any updates to the API
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 22/23] docs/devel: document some plugin assumptions
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (20 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 21/23] docs/devel: lift example and plugin API sections up Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
2024-02-16 16:30 ` [PATCH 23/23] docs/devel: plugins can trigger a tb flush Alex Bennée
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
While we attempt to hide implementation details from the plugin we
shouldn't be totally obtuse. Let the user know what they can and can't
expect with the various instrumentation options.
Message-Id: <20240103173349.398526-44-alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
docs/devel/tcg-plugins.rst | 49 ++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst
index 535a74684c5..9cc09d8c3da 100644
--- a/docs/devel/tcg-plugins.rst
+++ b/docs/devel/tcg-plugins.rst
@@ -112,6 +112,55 @@ details are opaque to plugins. The plugin is able to query select
details of instructions and system configuration only through the
exported *qemu_plugin* functions.
+However the following assumptions can be made:
+
+Translation Blocks
+++++++++++++++++++
+
+All code will go through a translation phase although not all
+translations will be necessarily be executed. You need to instrument
+actual executions to track what is happening.
+
+It is quite normal to see the same address translated multiple times.
+If you want to track the code in system emulation you should examine
+the underlying physical address (``qemu_plugin_insn_haddr``) to take
+into account the effects of virtual memory although if the system does
+paging this will change too.
+
+Not all instructions in a block will always execute so if its
+important to track individual instruction execution you need to
+instrument them directly. However asynchronous interrupts will not
+change control flow mid-block.
+
+Instructions
+++++++++++++
+
+Instruction instrumentation runs before the instruction executes. You
+can be can be sure the instruction will be dispatched, but you can't
+be sure it will complete. Generally this will be because of a
+synchronous exception (e.g. SIGILL) triggered by the instruction
+attempting to execute. If you want to be sure you will need to
+instrument the next instruction as well. See the ``execlog.c`` plugin
+for examples of how to track this and finalise details after execution.
+
+Memory Accesses
++++++++++++++++
+
+Memory callbacks are called after a successful load or store.
+Unsuccessful operations (i.e. faults) will not be visible to memory
+instrumentation although the execution side effects can be observed
+(e.g. entering a exception handler).
+
+System Idle and Resume States
++++++++++++++++++++++++++++++
+
+The ``qemu_plugin_register_vcpu_idle_cb`` and
+``qemu_plugin_register_vcpu_resume_cb`` functions can be used to track
+when CPUs go into and return from sleep states when waiting for
+external I/O. Be aware though that these may occur less frequently
+than in real HW due to the inefficiencies of emulation giving less
+chance for the CPU to idle.
+
Internals
---------
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH 23/23] docs/devel: plugins can trigger a tb flush
2024-02-16 16:30 [PATCH 00/23] maintainer updates for 9.0 pre-PR (tests, plugin register support) Alex Bennée
` (21 preceding siblings ...)
2024-02-16 16:30 ` [PATCH 22/23] docs/devel: document some plugin assumptions Alex Bennée
@ 2024-02-16 16:30 ` Alex Bennée
22 siblings, 0 replies; 38+ messages in thread
From: Alex Bennée @ 2024-02-16 16:30 UTC (permalink / raw)
To: qemu-devel
Cc: Yoshinori Sato, David Hildenbrand, Weiwei Li, Richard Henderson,
Michael Rolnik, Ilya Leoshkevich, Peter Maydell, qemu-ppc,
Paolo Bonzini, qemu-riscv, Cleber Rosa, Thomas Huth, Song Gao,
qemu-arm, Pierrick Bouvier, John Snow, Alex Bennée,
Cédric Le Goater, Nicholas Piggin, qemu-s390x,
Laurent Vivier, Edgar E. Iglesias, Daniel Henrique Barboza,
Yanan Wang, Palmer Dabbelt, Marcel Apfelbaum, Brian Cain,
Mahmoud Mandour, Alexandre Iooss, Bin Meng,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Eduardo Habkost, Alistair Francis, Liu Zhiwei
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
When scoreboards need to be reallocated.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213094009.150349-8-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
docs/devel/multi-thread-tcg.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst
index 7302c3bf534..1420789fff3 100644
--- a/docs/devel/multi-thread-tcg.rst
+++ b/docs/devel/multi-thread-tcg.rst
@@ -109,6 +109,7 @@ including:
- debugging operations (breakpoint insertion/removal)
- some CPU helper functions
- linux-user spawning its first thread
+ - operations related to TCG Plugins
This is done with the async_safe_run_on_cpu() mechanism to ensure all
vCPUs are quiescent when changes are being made to shared global
--
2.39.2
^ permalink raw reply related [flat|nested] 38+ messages in thread