From: Richard Henderson <richard.henderson@linaro.org>
To: "Víctor Colombo" <victor.colombo@eldorado.org.br>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: danielhb413@gmail.com, matheus.ferst@eldorado.org.br,
groug@kaod.org, david@gibson.dropbear.id.au, clg@kaod.org
Subject: Re: [PATCH] target/ppc: Change VSX instructions behavior to fill with zeros
Date: Sun, 6 Feb 2022 11:36:21 +1100 [thread overview]
Message-ID: <a5fe4228-fb40-607b-8c07-0ae79e4d0c43@linaro.org> (raw)
In-Reply-To: <20220204181944.65063-1-victor.colombo@eldorado.org.br>
On 2/5/22 05:19, Víctor Colombo wrote:
> ISA v3.1 changed some VSX instructions behavior by changing what the
> other words/doubleword in the result should contain when the result is
> only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and
> saves the result also in doubleword 0.
> Before, the second doubleword result was undefined according to the
> ISA, but now it's stated that it should be zeroed.
>
> Even tough the result was undefined before, hardware implementing these
> instructions already filled these fields with 0s. Changing every ISA
> version in QEMU to this behavior makes the results match what happens
> in hardware.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
>
> ---
>
> This patch is a proposal on a previous RFC I sent on this topic [1].
> I preferred this approach because it makes QEMU behavior closer to the
> real hardware.
>
> The affected instructions have the following note in the ISA:
>
> """
> Previous versions of the architecture allowed the
> contents of doubleword 1 of the result register to be
> undefined. However, all processors that support
> this instruction write 0s into doubleword 1 of the
> result register, as is required by this version of the
> architecture.
> """
>
> This patch is not exhaustive as
> 1. some instructions that had its behavior changed are not 'corrected'
> by this patch (mostly multiply-add instructions);
> 2. some instructions changed the behavior to also replicate the result
> in the other word from the doubleword if the result is a single
> word e.g. xscvdpuxws. So, this patch only focus on the 'zeroing'
> part, not the replication;
>
> Best regards,
>
> -- Víctor
>
> [1]https://lists.gnu.org/archive/html/qemu-ppc/2021-12/msg00198.html
> ---
> target/ppc/fpu_helper.c | 26 +++++++++++++-------------
> target/ppc/translate/vsx-impl.c.inc | 4 +++-
> 2 files changed, 16 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-02-06 0:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-04 18:19 [PATCH] target/ppc: Change VSX instructions behavior to fill with zeros Víctor Colombo
2022-02-06 0:36 ` Richard Henderson [this message]
2022-02-09 7:45 ` Cédric Le Goater
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