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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH] target/ppc: Change VSX instructions behavior to fill with zeros Content-Language: en-US To: =?UTF-8?Q?V=c3=adctor_Colombo?= , qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20220204181944.65063-1-victor.colombo@eldorado.org.br> From: Richard Henderson In-Reply-To: <20220204181944.65063-1-victor.colombo@eldorado.org.br> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, matheus.ferst@eldorado.org.br, groug@kaod.org, david@gibson.dropbear.id.au, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/5/22 05:19, Víctor Colombo wrote: > ISA v3.1 changed some VSX instructions behavior by changing what the > other words/doubleword in the result should contain when the result is > only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and > saves the result also in doubleword 0. > Before, the second doubleword result was undefined according to the > ISA, but now it's stated that it should be zeroed. > > Even tough the result was undefined before, hardware implementing these > instructions already filled these fields with 0s. Changing every ISA > version in QEMU to this behavior makes the results match what happens > in hardware. > > Signed-off-by: Víctor Colombo > > --- > > This patch is a proposal on a previous RFC I sent on this topic [1]. > I preferred this approach because it makes QEMU behavior closer to the > real hardware. > > The affected instructions have the following note in the ISA: > > """ > Previous versions of the architecture allowed the > contents of doubleword 1 of the result register to be > undefined. However, all processors that support > this instruction write 0s into doubleword 1 of the > result register, as is required by this version of the > architecture. > """ > > This patch is not exhaustive as > 1. some instructions that had its behavior changed are not 'corrected' > by this patch (mostly multiply-add instructions); > 2. some instructions changed the behavior to also replicate the result > in the other word from the doubleword if the result is a single > word e.g. xscvdpuxws. So, this patch only focus on the 'zeroing' > part, not the replication; > > Best regards, > > -- Víctor > > [1]https://lists.gnu.org/archive/html/qemu-ppc/2021-12/msg00198.html > --- > target/ppc/fpu_helper.c | 26 +++++++++++++------------- > target/ppc/translate/vsx-impl.c.inc | 4 +++- > 2 files changed, 16 insertions(+), 14 deletions(-) Reviewed-by: Richard Henderson r~