From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:37993) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gygCC-00033u-6r for qemu-devel@nongnu.org; Tue, 26 Feb 2019 12:07:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gygCB-0000aO-5h for qemu-devel@nongnu.org; Tue, 26 Feb 2019 12:07:08 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:39720) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gygCA-0008Uq-Ri for qemu-devel@nongnu.org; Tue, 26 Feb 2019 12:07:07 -0500 Received: by mail-pg1-x543.google.com with SMTP id h8so5988068pgp.6 for ; Tue, 26 Feb 2019 09:06:41 -0800 (PST) References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> <1551183797-13570-6-git-send-email-mateja.marjanovic@rt-rk.com> From: Richard Henderson Message-ID: Date: Tue, 26 Feb 2019 09:06:38 -0800 MIME-Version: 1.0 In-Reply-To: <1551183797-13570-6-git-send-email-mateja.marjanovic@rt-rk.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mateja Marjanovic , qemu-devel@nongnu.org Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net On 2/26/19 4:23 AM, Mateja Marjanovic wrote: > + } else if (rd == rt) { > + TCGv_i64 t0 = tcg_temp_new(); > + TCGv_i64 t1 = tcg_temp_new(); > + uint64_t mask0 = (1ULL << 16) - 1; > + uint64_t mask1 = mask0 << 16; > + uint64_t mask2 = mask1 << 16; > + uint64_t mask3 = (mask2 << 16) | mask0; > + > + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1); > + tcg_gen_shli_i64(t0, t0, 16); > + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2); > + tcg_gen_shri_i64(t1, t1, 16); > + > + tcg_gen_andi_i64(cpu_gpr[rt], cpu_gpr[rt], mask3); > + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0); > + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1); > + > + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1); > + tcg_gen_shli_i64(t0, t0, 16); > + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2); > + tcg_gen_shri_i64(t1, t1, 16); > + > + tcg_gen_andi_i64(cpu_mmr[rt], cpu_mmr[rt], mask3); > + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0); > + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1); > + > + tcg_temp_free(t0); > + tcg_temp_free(t1); > + } else { > + TCGv_i64 t0 = tcg_temp_new(); > + TCGv_i64 t1 = tcg_temp_new(); > + uint64_t mask0 = (1ULL << 16) - 1; > + uint64_t mask1 = mask0 << 16; > + uint64_t mask2 = mask1 << 16; > + uint64_t mask3 = mask2 << 16; > + > + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3); > + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2); > + tcg_gen_shri_i64(t1, t1, 16); > + tcg_gen_or_i64(t0, t0, t1); > + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1); > + tcg_gen_shli_i64(t1, t1, 16); > + tcg_gen_or_i64(t0, t0, t1); > + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0); > + tcg_gen_or_i64(t0, t0, t1); > + > + tcg_gen_mov_i64(cpu_gpr[rd], t0); > + > + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3); > + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2); > + tcg_gen_shri_i64(t1, t1, 16); > + tcg_gen_or_i64(t0, t0, t1); > + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1); > + tcg_gen_shli_i64(t1, t1, 16); > + tcg_gen_or_i64(t0, t0, t1); > + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0); > + tcg_gen_or_i64(t0, t0, t1); > + > + tcg_gen_mov_i64(cpu_mmr[rd], t0); > + > + tcg_temp_free(t0); > + tcg_temp_free(t1); > + } The code for rd != rt will work just fine for rd == rt. Why are you doubling the amount of code you are writing? r~