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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-devel@nongnu.org
Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org
Subject: Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers
Date: Thu, 23 Jul 2020 20:59:31 -0700	[thread overview]
Message-ID: <a624b5cc-bee5-76c6-35ce-008a4bf9f0ca@linaro.org> (raw)
In-Reply-To: <abf8bc3d-b021-6d01-3b7d-fa42bfe64653@c-sky.com>

On 7/23/20 7:47 PM, LIU Zhiwei wrote:
> 
> 
> On 2020/7/24 8:28, Richard Henderson wrote:
>> If a 32-bit input is not properly nanboxed, then the input is
>> replaced with the default qnan.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/riscv/internals.h  | 11 +++++++
>>   target/riscv/fpu_helper.c | 64 ++++++++++++++++++++++++++++-----------
>>   2 files changed, 57 insertions(+), 18 deletions(-)
>>
>> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
>> index 9f4ba7d617..f1a546dba6 100644
>> --- a/target/riscv/internals.h
>> +++ b/target/riscv/internals.h
>> @@ -43,4 +43,15 @@ static inline uint64_t nanbox_s(float32 f)
>>       return f | MAKE_64BIT_MASK(32, 32);
>>   }
>>   +static inline float32 check_nanbox_s(uint64_t f)
>> +{
>> +    uint64_t mask = MAKE_64BIT_MASK(32, 32);
>> +
>> +    if (likely((f & mask) == mask)) {
>> +        return (uint32_t)f;
>> +    } else {
>> +        return 0x7fc00000u; /* default qnan */
>> +    }
>> +}
>> +
> If possible,
> 
> +static inline float32 check_nanbox(uint64_t f, uint32_t flen)
> +{
> +    uint64_t mask = MAKE_64BIT_MASK(flen, 64 - flen);
> +
> +    if (likely((f & mask) == mask)) {
> +        return (uint32_t)f;
> +    } else {
> +        return (flen == 32) ? 0x7fc00000u : 0x7e00u; /* default qnan */
> +    }
> +}

The difficulty of choosing the proper default qnan is an example of why we
should *not* attempt to make this function fully general, but should instead
define separate functions for each type.  E.g.

static inline float16 check_nanbox_h(uint64_t f);
static inline bfloat16 check_nanbox_b(uint64_t f);


r~


  reply	other threads:[~2020-07-24  4:00 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-24  0:28 [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison Richard Henderson
2020-07-24  0:28 ` [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers Richard Henderson
2020-07-24  2:35   ` LIU Zhiwei
2020-07-24  3:55     ` Richard Henderson
2020-07-24  6:05       ` LIU Zhiwei
2020-08-06  6:09         ` Chih-Min Chao
2020-08-06  7:05           ` LIU Zhiwei
2020-08-06  8:42             ` Chih-Min Chao
2020-08-06 10:02               ` LIU Zhiwei
2020-07-24  0:28 ` [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Richard Henderson
2020-07-24  2:39   ` LIU Zhiwei
2020-08-06  6:24   ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c Richard Henderson
2020-07-24  2:41   ` LIU Zhiwei
2020-08-06  6:24   ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers Richard Henderson
2020-07-24  2:47   ` LIU Zhiwei
2020-07-24  3:59     ` Richard Henderson [this message]
2020-08-06  6:26   ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c Richard Henderson
2020-07-24  6:04   ` LIU Zhiwei
2020-08-06  6:27   ` Chih-Min Chao
2020-08-07 20:24   ` Chih-Min Chao
2020-08-08 14:18     ` LIU Zhiwei
2020-08-08 23:06       ` LIU Zhiwei
2020-07-24  0:28 ` [PATCH v2 6/7] target/riscv: Clean up fmv.w.x Richard Henderson
2020-08-06  6:28   ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 7/7] target/riscv: check before allocating TCG temps Richard Henderson
2020-08-06  6:28   ` Chih-Min Chao
2020-07-24  2:31 ` [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison LIU Zhiwei
2020-07-27 23:37 ` Alistair Francis

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