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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
	qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Date: Thu, 14 Oct 2021 09:01:07 -0700	[thread overview]
Message-ID: <a64a991f-8692-8dd5-c69e-6541a2e60e06@linaro.org> (raw)
In-Reply-To: <fe624f35-b12a-ad57-fabd-9eb47a0e3c6f@c-sky.com>

On 10/14/21 12:08 AM, LIU Zhiwei wrote:
> 
> On 2021/10/14 上午4:50, Richard Henderson wrote:
>> Shortly, the set of supported XL will not be just 32 and 64,
>> and representing that properly using the enumeration will be
>> imperative.
>>
>> Two places, booting and gdb, intentionally use misa_mxl_max
>> to emphasize the use of the reset value of misa.mxl, and not
>> the current cpu state.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/riscv/cpu.h            |  9 ++++++++-
>>   hw/riscv/boot.c               |  2 +-
>>   semihosting/arm-compat-semi.c |  2 +-
>>   target/riscv/cpu.c            | 24 ++++++++++++++----------
>>   target/riscv/cpu_helper.c     | 12 ++++++------
>>   target/riscv/csr.c            | 24 ++++++++++++------------
>>   target/riscv/gdbstub.c        |  2 +-
>>   target/riscv/monitor.c        |  4 ++--
>>   8 files changed, 45 insertions(+), 34 deletions(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index e708fcc168..87248b562a 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1)
>>   FIELD(TB_FLAGS, HLSX, 9, 1)
>>   FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
>> -bool riscv_cpu_is_32bit(CPURISCVState *env);
>> +#ifdef CONFIG_RISCV32
>> +#define riscv_cpu_mxl(env)      MXL_RV32
>> +#else
>> +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>> +{
>> +    return env->misa_mxl;
>> +}
>> +#endif
> 
> Hi Richard,
> 
> I don't know why we use CONFIG_RISCV32 here. I looked through the target source code. It 
> doesn't use this macro before.

Typo, should be TARGET_RISCV32.

But the reason to have the ifdef is so that riscv_cpu_mxl becomes a constant and the 
compiler can fold away more code.

>>   bool riscv_is_32bit(RISCVHartArrayState *harts)
>>   {
>> -    return riscv_cpu_is_32bit(&harts->harts[0].env);
>> +    return harts->harts[0].env.misa_mxl_max == MXL_RV32;
> 
> Why not use  misa_mxl  here?  As this is just a replacement of riscv_cpu_is_32bit like 
> many other places.

It isn't clear to me that all uses of this are at boot time.  Once MXL may be changed at 
runtime, that (potentially) changes this test, and it seems unlikely that the board would 
really change based on the current status of the cpu.


r~


  reply	other threads:[~2021-10-14 16:23 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14  7:52   ` LIU Zhiwei
2021-10-14 15:52     ` Richard Henderson
2021-10-15  5:01   ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14  7:08   ` LIU Zhiwei
2021-10-14 16:01     ` Richard Henderson [this message]
2021-10-15  5:05   ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14  8:20   ` LIU Zhiwei
2021-10-14 16:12     ` Richard Henderson
2021-10-15 12:37   ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14  5:54   ` LIU Zhiwei
2021-10-15  5:08   ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-14  5:55   ` LIU Zhiwei
2021-10-15  5:09   ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-14  8:26   ` LIU Zhiwei
2021-10-15  5:11   ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14  8:40   ` LIU Zhiwei
2021-10-14  8:57     ` Frédéric Pétrot
2021-10-14 15:39       ` Richard Henderson
2021-10-15  5:19   ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-15  5:21   ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson

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