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([2602:ae:1541:f901:b714:1fce:85fa:2fc7]) by smtp.gmail.com with ESMTPSA id h18-20020a635752000000b0050301745a5dsm2155728pgm.50.2023.03.31.18.52.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 31 Mar 2023 18:52:59 -0700 (PDT) Message-ID: Date: Fri, 31 Mar 2023 18:52:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v4 6/8] accel/tcg: Fix tb mis-matched problem when CF_PCREL is enabled Content-Language: en-US From: Richard Henderson To: Weiwei Li , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20230331150609.114401-1-liweiwei@iscas.ac.cn> <20230331150609.114401-7-liweiwei@iscas.ac.cn> <3cf2469f-fd47-544d-1343-663a5e6c5b8d@linaro.org> In-Reply-To: <3cf2469f-fd47-544d-1343-663a5e6c5b8d@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/31/23 18:26, Richard Henderson wrote: > On 3/31/23 08:06, Weiwei Li wrote: >> A corner case is triggered  when tb block with first_pc = 0x80000008 >> and first_pc = 0x800000200 has the same jump cache hash, and share >> the same tb entry with the same tb information except PC. >> The executed sequence is as follows: >> tb(0x80000008) -> tb(0x80000008)-> tb(0x800000200) -> tb(0x80000008) >> >> 1. At the first time tb for 0x80000008 is loaded, tb in jmp_cache is >> filled, however pc is not updated. >> 2. At the second time tb for 0x80000008 is looked up in tb_lookup(), >> pc in jmp cache is set to 0x80000008. >> 3. when tb for 0x800000200 is loaded, tb for jmp cache is updated to >> this block, however pc is not updated, and remains to be 0x80000008. >> 4. Finally at the last time tb for 0x80000008 is looked up, tb for >> 0x800000200 is mismatched. >> >> Signed-off-by: Weiwei Li >> Signed-off-by: Junqiang Wang >> --- >>   accel/tcg/cpu-exec.c | 3 +++ >>   1 file changed, 3 insertions(+) >> >> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c >> index c815f2dbfd..faff413f42 100644 >> --- a/accel/tcg/cpu-exec.c >> +++ b/accel/tcg/cpu-exec.c >> @@ -983,6 +983,9 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) >>                   h = tb_jmp_cache_hash_func(pc); >>                   /* Use the pc value already stored in tb->pc. */ >>                   qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); >> +                if (cflags & CF_PCREL) { >> +                    qatomic_set(&cpu->tb_jmp_cache->array[h].pc, pc); >> +                } > > Good catch on the bug, but incorrect fix.  Need > > if (cflags & CF_PCREL) { >     qatomic_set(&cpu->tb_jmp_cache->array[h].pc, pc); >     qatomic_store_release(&cpu->tb_jmp_cache->array[h].tb, tb); > } else { >     /* Use the pc value already stored in tb->pc. */ >     qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); > } Queuing the fix to tcg-next. r~