From: Jiajie Chen <c@jia.je>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: gaosong@loongson.cn, git@xen0n.name
Subject: Re: [PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Date: Sat, 2 Sep 2023 09:06:00 +0800 [thread overview]
Message-ID: <a6ce39a5-c128-3b5e-f412-b13a0328e328@jia.je> (raw)
In-Reply-To: <39e63387-dad7-ffd0-12c3-082f81c09997@linaro.org>
On 2023/9/2 01:48, Richard Henderson wrote:
> On 9/1/23 10:28, Jiajie Chen wrote:
>>
>> On 2023/9/2 01:24, Richard Henderson wrote:
>>> On 9/1/23 02:30, Jiajie Chen wrote:
>>>> Signed-off-by: Jiajie Chen <c@jia.je>
>>>> ---
>>>> tcg/loongarch64/tcg-target-con-set.h | 1 +
>>>> tcg/loongarch64/tcg-target.c.inc | 60
>>>> ++++++++++++++++++++++++++++
>>>> 2 files changed, 61 insertions(+)
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>
>>>
>>>>
>>>> diff --git a/tcg/loongarch64/tcg-target-con-set.h
>>>> b/tcg/loongarch64/tcg-target-con-set.h
>>>> index 37b3f80bf9..d04916db25 100644
>>>> --- a/tcg/loongarch64/tcg-target-con-set.h
>>>> +++ b/tcg/loongarch64/tcg-target-con-set.h
>>>> @@ -31,4 +31,5 @@ C_O1_I2(r, 0, rZ)
>>>> C_O1_I2(r, rZ, ri)
>>>> C_O1_I2(r, rZ, rJ)
>>>> C_O1_I2(r, rZ, rZ)
>>>> +C_O1_I2(w, w, wJ)
>>>
>>> Notes for improvement: 'J' is a signed 32-bit immediate.
>>
>>
>> I was wondering about the behavior of 'J' on i128 types: in
>> tcg_target_const_match(), the argument type is int, so will the
>> higher bits be truncated?
>
> The argument is int64_t val.
>
> The only constants that we allow for vectors are dupi, so all higher
> parts are the same as the lower part.
Consider the following scenario:
cmp_vec v128,e32,tmp4,tmp3,v128$0xffffffffffffffff
cmp_vec v128,e32,tmp4,tmp3,v128$0xfffffffefffffffe
cmp_vec v128,e8,tmp4,tmp3,v128$0xfefefefefefefefe
When matching constant constraint, the vector element width is unknown,
so it cannot decide whether 0xfefefefefefefefe means e8 0xfe or e16 0xfefe.
>
>> Besides, tcg_target_const_match() does not know the vector element
>> width.
>
> No, it hadn't been required so far -- there are very few vector
> instructions that allow immediates.
>
>
> r~
next prev parent reply other threads:[~2023-09-02 1:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 9:30 [PATCH v2 00/14] Lower TCG vector ops to LSX Jiajie Chen
2023-09-01 9:30 ` [PATCH v2 01/14] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-01 17:06 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 02/14] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-01 17:05 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-01 17:24 ` Richard Henderson
2023-09-01 17:28 ` Jiajie Chen
2023-09-01 17:48 ` Richard Henderson
2023-09-02 1:06 ` Jiajie Chen [this message]
2023-09-01 9:30 ` [PATCH v2 04/14] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-01 17:58 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 05/14] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-01 17:59 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 06/14] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 07/14] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 08/14] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 09/14] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 10/14] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-01 18:01 ` Richard Henderson
2023-09-01 9:31 ` [PATCH v2 13/14] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-01 18:02 ` Richard Henderson
2023-09-01 9:31 ` [PATCH v2 14/14] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-01 18:06 ` Richard Henderson
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