Re: [PATCH] target/riscv: Don't start user-mode with VILL

[Richard Henderson <richard.henderson@linaro.org>]

On 11/21/24 18:32, Palmer Dabbelt wrote:
> This is still under discussion in the psABI, but it's looking like we're
> going to forbid VILL in userspace in order to maintain compatibility
> with binaries that don't expect implementations to trap whole register
> moves under VILL (as in QEMU before 4eff52cd46 ("target/riscv: Add vill
> check for whole vector register move instructions"), for example).
> 
> Fixes: f8c1f36a2e ("target/riscv: Set vtype.vill on CPU reset")
> Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/454
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>   target/riscv/cpu.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f219f0c3b5..d19a44de99 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1022,7 +1022,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>       cs->exception_index = RISCV_EXCP_NONE;
>       env->load_res = -1;
>       set_default_nan_mode(1, &env->fp_status);
> +#ifdef CONFIG_USER_ONLY
> +    env->vill = false;
> +#else
>       env->vill = true;
> +#endif
>   
>   #ifndef CONFIG_USER_ONLY
>       if (cpu->cfg.debug) {

This suggests that vtype_check() in tcg/riscv/tcg-target.c.inc needs modification.  If the 
probe fails, we need to set vtype back to any valid value (e.g. 0).

Also, may I suggest stronger guidelines about which VSEW are required to be supported in 
various configurations.  Right now, it appears as if the static compilers simply assume 
all combinations of SEW/LMUL work.


r~