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Fri, 22 Nov 2024 07:36:30 -0800 (PST) Received: from [192.168.170.227] ([187.210.107.181]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71c03756313sm448919a34.9.2024.11.22.07.36.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Nov 2024 07:36:30 -0800 (PST) Message-ID: Date: Fri, 22 Nov 2024 09:36:27 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: Don't start user-mode with VILL To: Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20241122003247.8955-1-palmer@rivosinc.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241122003247.8955-1-palmer@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/21/24 18:32, Palmer Dabbelt wrote: > This is still under discussion in the psABI, but it's looking like we're > going to forbid VILL in userspace in order to maintain compatibility > with binaries that don't expect implementations to trap whole register > moves under VILL (as in QEMU before 4eff52cd46 ("target/riscv: Add vill > check for whole vector register move instructions"), for example). > > Fixes: f8c1f36a2e ("target/riscv: Set vtype.vill on CPU reset") > Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/454 > Signed-off-by: Palmer Dabbelt > --- > target/riscv/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f219f0c3b5..d19a44de99 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1022,7 +1022,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) > cs->exception_index = RISCV_EXCP_NONE; > env->load_res = -1; > set_default_nan_mode(1, &env->fp_status); > +#ifdef CONFIG_USER_ONLY > + env->vill = false; > +#else > env->vill = true; > +#endif > > #ifndef CONFIG_USER_ONLY > if (cpu->cfg.debug) { This suggests that vtype_check() in tcg/riscv/tcg-target.c.inc needs modification. If the probe fails, we need to set vtype back to any valid value (e.g. 0). Also, may I suggest stronger guidelines about which VSEW are required to be supported in various configurations. Right now, it appears as if the static compilers simply assume all combinations of SEW/LMUL work. r~