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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id b4sm9070341wrr.30.2020.12.10.04.59.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Dec 2020 04:59:34 -0800 (PST) Subject: Re: [PATCH v10 24/32] cpu: move cc->transaction_failed to tcg_ops To: Claudio Fontana , Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy References: <20201210121226.19822-1-cfontana@suse.de> <20201210121226.19822-25-cfontana@suse.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 10 Dec 2020 13:59:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20201210121226.19822-25-cfontana@suse.de> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/10/20 1:12 PM, Claudio Fontana wrote: > Signed-off-by: Claudio Fontana > Reviewed-by: Alex Bennée > --- > include/hw/core/cpu.h | 18 +++++++----------- > include/hw/core/tcg-cpu-ops.h | 10 ++++++++++ > hw/mips/jazz.c | 9 +++++++-- > target/alpha/cpu.c | 2 +- > target/arm/cpu.c | 4 ++-- > target/m68k/cpu.c | 2 +- > target/microblaze/cpu.c | 2 +- > target/mips/cpu.c | 2 +- > target/riscv/cpu.c | 2 +- > target/sparc/cpu.c | 2 +- > target/xtensa/cpu.c | 2 +- > 11 files changed, 33 insertions(+), 22 deletions(-) ... > diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h > index a7387b5c39..3cc2733410 100644 > --- a/include/hw/core/tcg-cpu-ops.h > +++ b/include/hw/core/tcg-cpu-ops.h > @@ -11,6 +11,7 @@ > #define TCG_CPU_OPS_H > > #include "hw/core/cpu.h" > +#include "exec/memattrs.h" > > /** > * struct TcgCpuOperations: TCG operations specific to a CPU class > @@ -41,6 +42,15 @@ typedef struct TcgCpuOperations { > /** @do_interrupt: Callback for interrupt handling. */ > void (*do_interrupt)(CPUState *cpu); > Do we want to restrict this handler to system-mode? #ifdef CONFIG_SOFTMMU > + /** > + * @do_transaction_failed: Callback for handling failed memory transactions > + * (ie bus faults or external aborts; not MMU faults) > + */ > + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, > + unsigned size, MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr); #endif > /** > * @tlb_fill: Handle a softmmu tlb miss or user-only address fault > * ...