From: Eric Auger <eric.auger@redhat.com>
To: Cornelia Huck <cohuck@redhat.com>,
eric.auger.pro@gmail.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, kvmarm@lists.linux.dev,
peter.maydell@linaro.org, richard.henderson@linaro.org,
alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev,
sebott@redhat.com, shameerali.kolothum.thodi@huawei.com,
armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,
jdenemar@redhat.com
Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com,
philmd@linaro.org, pbonzini@redhat.com
Subject: Re: [PATCH v3 06/10] arm/kvm: Allow reading all the writable ID registers
Date: Tue, 13 May 2025 16:31:30 +0200 [thread overview]
Message-ID: <a706e9a2-0a49-4296-ba0a-8001f433b8b8@redhat.com> (raw)
In-Reply-To: <20250414163849.321857-7-cohuck@redhat.com>
On 4/14/25 6:38 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> At the moment kvm_arm_get_host_cpu_features() reads a subset of the
> ID regs. As we want to introduce properties for all writable ID reg
> fields, we want more genericity and read more default host register
> values.
>
> Introduce a new get_host_cpu_idregs() helper and add a new exhaustive
> boolean parameter to kvm_arm_get_host_cpu_features() and
> kvm_arm_set_cpu_features_from_host() to select the right behavior.
> The host cpu model will keep the legacy behavior unless the writable
> id register interface is available.
>
> A writable_map IdRegMap is introduced in the CPU object. A subsequent
> patch will populate it.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-sysregs.h | 2 ++
> target/arm/cpu.h | 3 ++
> target/arm/cpu64.c | 2 +-
> target/arm/kvm.c | 78 ++++++++++++++++++++++++++++++++++++++--
> target/arm/kvm_arm.h | 9 +++--
> target/arm/trace-events | 1 +
> 6 files changed, 89 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> index e89a1105904c..367fab51f19e 100644
> --- a/target/arm/cpu-sysregs.h
> +++ b/target/arm/cpu-sysregs.h
> @@ -41,6 +41,8 @@ int get_sysreg_idx(ARMSysRegs sysreg);
>
> #ifdef CONFIG_KVM
> uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
> +int kvm_idx_to_idregs_idx(int kidx);
> +int idregs_idx_to_kvm_idx(ARMIDRegisterIdx idx);
> #endif
>
> #endif /* ARM_CPU_SYSREGS_H */
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 775a8aebc5d3..8717c5e7695b 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1088,6 +1088,9 @@ struct ArchCPU {
> */
> ARMIdRegsState writable_id_regs;
>
> + /* ID reg writable bitmask (KVM only) */
> + IdRegMap *writable_map;
as it is KVM only we may put it in ifdef CONFIG_KVM block above
> +
> /* QOM property to indicate we should use the back-compat CNTFRQ default */
> bool backcompat_cntfrq;
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 839442745ea4..60a709502697 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -757,7 +757,7 @@ static void aarch64_host_initfn(Object *obj)
> {
> #if defined(CONFIG_KVM)
> ARMCPU *cpu = ARM_CPU(obj);
> - kvm_arm_set_cpu_features_from_host(cpu);
> + kvm_arm_set_cpu_features_from_host(cpu, false);
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> aarch64_add_sve_properties(obj);
> aarch64_add_pauth_properties(obj);
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index 6e3cd06e9bc5..b07d5f16db50 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -41,6 +41,7 @@
> #include "hw/acpi/ghes.h"
> #include "target/arm/gtimer.h"
> #include "migration/blocker.h"
> +#include "cpu-custom.h"
>
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_INFO(DEVICE_CTRL),
> @@ -270,7 +271,73 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegisterIdx i
> return ret;
> }
>
> -static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> +int kvm_idx_to_idregs_idx(int kidx)
> +{
> + int op1, crm, op2;
> + ARMSysRegs sysreg;
> +
> + op1 = kidx / 64;
> + if (op1 == 2) {
> + op1 = 3;
> + }
> + crm = (kidx % 64) / 8;
> + op2 = kidx % 8;
> + sysreg = ENCODE_ID_REG(3, op1, 0, crm, op2);
> + return get_sysreg_idx(sysreg);
> +}
> +
> +int idregs_idx_to_kvm_idx(ARMIDRegisterIdx idx)
> +{
> + ARMSysRegs sysreg = id_register_sysreg[idx];
> +
> + return KVM_ARM_FEATURE_ID_RANGE_IDX((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT);
> +}
> +
> +
> +/*
> + * get_host_cpu_idregs: Read all the writable ID reg host values
> + *
> + * Need to be called once the writable mask has been populated
> + * Note we may want to read all the known id regs but some of them are not
> + * writable and return an error, hence the choice of reading only those which
> + * are writable. Those are also readable!
> + */
> +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ahcf)
> +{
> + int err = 0;
> + int i;
> +
> + for (i = 0; i < NUM_ID_IDX; i++) {
> + ARM64SysReg *sysregdesc = &arm64_id_regs[i];
> + ARMSysRegs sysreg = sysregdesc->sysreg;
> + uint64_t writable_mask = cpu->writable_map->regs[idregs_idx_to_kvm_idx(i)];
> + uint64_t *reg;
> + int ret;
> +
> + if (!writable_mask) {
> + continue;
> + }
> +
> + reg = &ahcf->isar.idregs[i];
> + ret = read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg));
> + trace_get_host_cpu_idregs(sysregdesc->name, *reg);
> + if (ret) {
> + error_report("%s error reading value of host %s register (%m)",
> + __func__, sysregdesc->name);
> +
> + err = ret;
> + }
> + }
> + return err;
> +}
> +
> +static bool
> +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf,
> + bool exhaustive)
maybe the exhaustive term shall be replaced by handle_writable_id_regs
which tells more explicitly what it does
> {
> /* Identify the feature bits corresponding to the host CPU, and
> * fill out the ARMHostCPUClass fields accordingly. To do this
> @@ -398,6 +465,11 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> err |= get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX);
> err |= get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX);
>
> + /* Make sure writable ID reg values are read */
> + if (exhaustive) {
> + err |= get_host_cpu_idregs(cpu, fd, ahcf);
> + }
> +
> /*
> * DBGDIDR is a bit complicated because the kernel doesn't
> * provide an accessor for it in 64-bit mode, which is what this
> @@ -467,13 +539,13 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> return true;
> }
>
> -void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
> +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, bool exhaustive)
> {
> CPUARMState *env = &cpu->env;
>
> if (!arm_host_cpu_features.dtb_compatible) {
> if (!kvm_enabled() ||
> - !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) {
> + !kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features, exhaustive)) {
> /* We can't report this error yet, so flag that we need to
> * in arm_cpu_realizefn().
> */
> diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
> index 8d1f20ca8d89..90ba4f7d8987 100644
> --- a/target/arm/kvm_arm.h
> +++ b/target/arm/kvm_arm.h
> @@ -141,8 +141,12 @@ uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu);
> *
> * Set up the ARMCPU struct fields up to match the information probed
> * from the host CPU.
> + *
> + * @cpu: cpu object
> + * @exhaustive: if true, all the feature ID regs are queried instead of
s/queried/handled
> + * a subset
> */
> -void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
> +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, bool exhaustive);
>
> /**
> * kvm_arm_add_vcpu_properties:
> @@ -257,7 +261,8 @@ static inline int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idregmap)
> /*
> * These functions should never actually be called without KVM support.
> */
> -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
> +static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu,
> + bool exhaustive)
> {
> g_assert_not_reached();
> }
> diff --git a/target/arm/trace-events b/target/arm/trace-events
> index 4438dce7becc..17e52c0705f2 100644
> --- a/target/arm/trace-events
> +++ b/target/arm/trace-events
> @@ -13,3 +13,4 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
>
> # kvm.c
> kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64
> +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host value for %s is 0x%"PRIx64
Eric
next prev parent reply other threads:[~2025-05-13 14:32 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-14 16:38 [PATCH v3 00/10] kvm/arm: Introduce a customizable aarch64 KVM host model Cornelia Huck
2025-04-14 16:38 ` [PATCH v3 01/10] arm/cpu: Add infra to handle generated ID register definitions Cornelia Huck
2025-05-13 13:52 ` Eric Auger
2025-05-13 14:05 ` Cornelia Huck
2025-05-13 15:12 ` Eric Auger
2025-04-14 16:38 ` [PATCH v3 02/10] arm/cpu: Add sysreg properties generation Cornelia Huck
2025-04-15 7:09 ` Philippe Mathieu-Daudé
2025-04-15 7:20 ` Philippe Mathieu-Daudé
2025-05-19 14:49 ` Cornelia Huck
2025-05-13 15:23 ` Daniel P. Berrangé
2025-05-14 15:25 ` Cornelia Huck
2025-05-14 15:29 ` Daniel P. Berrangé
2025-04-14 16:38 ` [PATCH v3 03/10] arm/cpu: Add generated sysreg properties Cornelia Huck
2025-04-14 16:38 ` [PATCH v3 04/10] kvm: kvm_get_writable_id_regs Cornelia Huck
2025-05-13 14:20 ` Eric Auger
2025-05-13 14:42 ` Cornelia Huck
2025-05-13 15:16 ` Eric Auger
2025-04-14 16:38 ` [PATCH v3 05/10] arm/cpu: accessors for writable id registers Cornelia Huck
2025-04-29 16:27 ` Sebastian Ott
2025-04-30 13:48 ` Cornelia Huck
2025-04-14 16:38 ` [PATCH v3 06/10] arm/kvm: Allow reading all the writable ID registers Cornelia Huck
2025-05-13 14:31 ` Eric Auger [this message]
2025-05-16 14:17 ` Cornelia Huck
2025-05-20 14:05 ` Cornelia Huck
2025-05-23 8:27 ` Shameerali Kolothum Thodi via
2025-05-26 12:37 ` Cornelia Huck
2025-04-14 16:38 ` [PATCH v3 07/10] arm/kvm: write back modified ID regs to KVM Cornelia Huck
2025-04-15 7:03 ` Philippe Mathieu-Daudé
2025-04-15 9:54 ` Cornelia Huck
2025-05-13 14:33 ` Eric Auger
2025-07-02 4:01 ` Jinqian Yang via
2025-07-02 8:46 ` Cornelia Huck
2025-04-14 16:38 ` [PATCH v3 08/10] arm/cpu: more customization for the kvm host cpu model Cornelia Huck
2025-05-13 14:47 ` Eric Auger
2025-05-13 15:56 ` Daniel P. Berrangé
2025-05-16 14:42 ` Cornelia Huck
2025-05-13 15:59 ` Daniel P. Berrangé
2025-05-14 15:36 ` Cornelia Huck
2025-05-14 18:22 ` Daniel P. Berrangé
2025-05-16 14:51 ` Cornelia Huck
2025-05-16 14:57 ` Daniel P. Berrangé
2025-05-16 15:13 ` Cornelia Huck
2025-04-14 16:38 ` [PATCH v3 09/10] arm-qmp-cmds: introspection for ID register props Cornelia Huck
2025-05-13 14:50 ` Eric Auger
2025-04-14 16:38 ` [PATCH v3 10/10] arm/cpu-features: document ID reg properties Cornelia Huck
2025-05-13 15:09 ` Eric Auger
2025-05-13 16:23 ` Daniel P. Berrangé
2025-05-13 15:29 ` [PATCH v3 00/10] kvm/arm: Introduce a customizable aarch64 KVM host model Eric Auger
2025-05-14 13:47 ` Shameerali Kolothum Thodi via
2025-05-14 14:47 ` Eric Auger
2025-05-23 13:23 ` Shameerali Kolothum Thodi via
2025-05-26 12:44 ` Cornelia Huck
2025-05-27 10:06 ` Cornelia Huck
2025-06-03 15:14 ` Cornelia Huck
2025-06-04 10:58 ` Shameerali Kolothum Thodi via
2025-06-04 12:35 ` Cornelia Huck
2025-06-04 13:45 ` Shameerali Kolothum Thodi via
2025-06-05 16:31 ` Cornelia Huck
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