From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
To: qemu-devel@nongnu.org
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
alistair.francis@xilinx.com, zach.pfeffer@xilinx.com,
jues@xilinx.com
Subject: [Qemu-devel] [PATCH target-arm v2 05/13] arm: Implement uniprocessor with MP config
Date: Fri, 12 Jun 2015 12:10:35 -0700 [thread overview]
Message-ID: <a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwaite@xilinx.com> (raw)
In-Reply-To: <cover.1434066412.git.peter.crosthwaite@xilinx.com>
Add a boolean for indicating uniprocessors with MP extensions. This
drives the U bit in MPIDR. Prepares support for Cortex-R5.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
target-arm/cpu-qom.h | 3 +++
target-arm/helper.c | 9 ++++++---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index ed5a644..19c8e9c 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -116,6 +116,9 @@ typedef struct ARMCPU {
/* KVM init features for this CPU */
uint32_t kvm_init_features[7];
+ /* Uniprocessor system with MP extensions */
+ bool mp_is_up;
+
/* The instance init functions for implementation-specific subclasses
* set these fields to specify the implementation-dependent values of
* various constant registers and reset values of non-constant
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 88e59a7..8c6bc0c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2068,7 +2068,8 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
uint32_t mpidr = cs->cpu_index;
/* We don't support setting cluster ID ([8..11]) (known as Aff1
* in later ARM ARM versions), or any of the higher affinity level fields,
@@ -2078,9 +2079,11 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
mpidr |= (1U << 31);
/* Cores which are uniprocessor (non-coherent)
* but still implement the MP extensions set
- * bit 30. (For instance, A9UP.) However we do
- * not currently model any of those cores.
+ * bit 30. (For instance, Cortex-R5).
*/
+ if (cpu->mp_is_up) {
+ mpidr |= (1u << 30);
+ }
}
return mpidr;
}
--
2.4.3.3.g905f831
next prev parent reply other threads:[~2015-06-12 19:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-12 19:10 [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMSA systems Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 02/13] arm: Don't add v7mp registers in MPU systems Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 03/13] arm: helper: Factor out CP regs common to [pv]msa Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 04/13] arm: Refactor get_phys_addr FSR return mechanism Peter Crosthwaite
2015-06-15 12:44 ` Peter Maydell
2015-06-12 19:10 ` Peter Crosthwaite [this message]
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 06/13] arm: Add has-mpu property Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 07/13] target-arm/helper.c: define MPUIR register Peter Crosthwaite
2015-06-15 13:44 ` Peter Maydell
2015-06-16 19:19 ` Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_addr_mpu Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 09/13] target-arm: Add registers for PMSAv7 Peter Crosthwaite
2015-06-15 14:04 ` Peter Maydell
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 10/13] target-arm: Implement PMSAv7 MPU Peter Crosthwaite
2015-06-15 14:42 ` Peter Maydell
2015-06-16 19:25 ` Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 11/13] target-arm: Add support for Cortex-R5 Peter Crosthwaite
2015-06-15 14:24 ` Peter Maydell
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 12/13] arm: xlnx-zynqmp: Preface CPU variables with "apu" Peter Crosthwaite
2015-06-12 19:10 ` [Qemu-devel] [PATCH target-arm v2 13/13] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs Peter Crosthwaite
2015-06-15 13:48 ` [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support Peter Maydell
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