From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3ULh-0007RZ-Uz for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3ULd-0003FE-60 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:41 -0400 Received: from mail-qc0-f174.google.com ([209.85.216.174]:33088) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3ULd-0003F8-32 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:37 -0400 Received: by qcnj1 with SMTP id j1so13319766qcn.0 for ; Fri, 12 Jun 2015 12:10:36 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Fri, 12 Jun 2015 12:10:35 -0700 Message-Id: In-Reply-To: References: Subject: [Qemu-devel] [PATCH target-arm v2 05/13] arm: Implement uniprocessor with MP config List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Signed-off-by: Peter Crosthwaite --- target-arm/cpu-qom.h | 3 +++ target-arm/helper.c | 9 ++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ed5a644..19c8e9c 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -116,6 +116,9 @@ typedef struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; + /* Uniprocessor system with MP extensions */ + bool mp_is_up; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target-arm/helper.c b/target-arm/helper.c index 88e59a7..8c6bc0c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2068,7 +2068,8 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); uint32_t mpidr = cs->cpu_index; /* We don't support setting cluster ID ([8..11]) (known as Aff1 * in later ARM ARM versions), or any of the higher affinity level fields, @@ -2078,9 +2079,11 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) mpidr |= (1U << 31); /* Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set - * bit 30. (For instance, A9UP.) However we do - * not currently model any of those cores. + * bit 30. (For instance, Cortex-R5). */ + if (cpu->mp_is_up) { + mpidr |= (1u << 30); + } } return mpidr; } -- 2.4.3.3.g905f831