From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
Chen Baozi <chenbaozi@phytium.com.cn>
Cc: qemu-devel@nongnu.org, "open list:ARM TCG CPUs" <qemu-arm@nongnu.org>
Subject: Re: [PATCH v2] target/arm: Add Neoverse-N1 registers
Date: Mon, 6 Mar 2023 18:29:28 +0100 [thread overview]
Message-ID: <a7192c74-be6b-fae5-b282-619d39380da7@linaro.org> (raw)
In-Reply-To: <5f8a1a7a-2971-029e-adc2-eef8a3c121ab@linaro.org>
W dniu 6.03.2023 o 18:13, Marcin Juszkiewicz pisze:
> W dniu 6.03.2023 o 16:37, Peter Maydell pisze:
> > On Mon, 6 Mar 2023 at 15:12, Chen Baozi <chenbaozi@phytium.com.cn>
> wrote:
> >>
> >> Add implementation defined registers for neoverse-n1 which
> >> would be accessed by TF-A. Since there is no DSU in Qemu,
> >> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
> >>
> >> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
> >> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> >
> > Did Marcin test this version of the patch ?
>
> Hard to test it without updating TF-A first to not use DSU. Older TF-A
> starts and then hangs.
>
> Waiting for Chen to provide patch to TF-A and will test.
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Adding neoverse_n_common.S turned out to be enough:
~ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 125.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x4
CPU part : 0xd0c
CPU revision : 1
next prev parent reply other threads:[~2023-03-06 17:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-06 15:12 [PATCH v2] target/arm: Add Neoverse-N1 registers Chen Baozi
2023-03-06 15:37 ` Peter Maydell
2023-03-06 17:13 ` Marcin Juszkiewicz
2023-03-06 17:29 ` Marcin Juszkiewicz [this message]
2023-03-06 15:43 ` Peter Maydell
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