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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 2/2] hw/mips: Add MIPS virt board
Date: Tue, 7 Mar 2023 15:32:38 +0100	[thread overview]
Message-ID: <a720d85a-8c16-f075-4525-ecf6ebbdd8fc@linaro.org> (raw)
In-Reply-To: <20230304223803.55764-3-jiaxun.yang@flygoat.com>

On 4/3/23 23:38, Jiaxun Yang wrote:
> MIPS virt board is design to utilize existing VirtIO infrastures
> but also comptitable with MIPS's existing internal simulation tools.
> 
> It includes virtio-pci, virtio-mmio, pcie gpex, flash rom, fw_cfg,
> goldfish-rtc and MIPS CPS system.
> 
> It should be able to cooperate with any MIPS CPU cores.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> v1:
>   - Rename to virt board
>   - Convert BIOS flash to ROM
>   - Cleanups
> v2:
>   - Fix fdt flash
>   - Remove UP variant
> ---
>   MAINTAINERS                             |   7 +
>   configs/devices/mips-softmmu/common.mak |   1 +
>   docs/system/target-mips.rst             |  22 +
>   hw/mips/Kconfig                         |  17 +
>   hw/mips/meson.build                     |   1 +
>   hw/mips/virt.c                          | 916 ++++++++++++++++++++++++
>   6 files changed, 964 insertions(+)
>   create mode 100644 hw/mips/virt.c


> +static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
> +{
> +    uint64_t regaddr;
> +    const MemMapEntry *memmap = virt_memmap;
> +
> +    /* Move CM GCRs */
> +    regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),

Eh this is odd C...

> +    bl_gen_write_ulong(&p, regaddr, memmap[VIRT_CM].base);
> +
> +    /* Move & enable GIC GCRs */
> +    regaddr = cpu_mips_phys_to_kseg1(NULL, memmap[VIRT_CM].base +
> +                                                GCR_GIC_BASE_OFS),
> +    bl_gen_write_ulong(&p, regaddr,
> +                        memmap[VIRT_GIC].base | GCR_GIC_BASE_GICEN_MSK);
> +
> +    /* Move & enable CPC GCRs */
> +    regaddr = cpu_mips_phys_to_kseg1(NULL, memmap[VIRT_CM].base +
> +                                                GCR_CPC_BASE_OFS),
> +    bl_gen_write_ulong(&p, regaddr,
> +                        memmap[VIRT_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
> +
> +    /*
> +     * Setup argument registers to follow the UHI boot protocol:
> +     *
> +     * a0/$4 = -2
> +     * a1/$5 = virtual address of FDT
> +     * a2/$6 = 0
> +     * a3/$7 = 0
> +     */
> +    bl_gen_jump_kernel(&p,
> +                       true, 0, true, (int32_t)-2,
> +                       true, fdt_addr, true, 0, true, 0,
> +                       kernel_entry);
> +}



  parent reply	other threads:[~2023-03-07 14:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-04 22:38 [PATCH v2 0/2] MIPS Virt machine Jiaxun Yang
2023-03-04 22:38 ` [PATCH v2 1/2] hw/misc: Add MIPS Trickbox device Jiaxun Yang
2023-03-04 22:38 ` [PATCH v2 2/2] hw/mips: Add MIPS virt board Jiaxun Yang
2023-03-06 16:42   ` Philippe Mathieu-Daudé
2023-03-06 16:51     ` Philippe Mathieu-Daudé
2023-03-07 14:32   ` Philippe Mathieu-Daudé [this message]
2023-03-07 20:10   ` Philippe Mathieu-Daudé
2023-03-07 21:09     ` Jiaxun Yang
2023-03-07 15:01 ` [PATCH v2 0/2] MIPS Virt machine Philippe Mathieu-Daudé
2023-03-07 20:07   ` Jiaxun Yang
2023-03-07 20:14     ` Philippe Mathieu-Daudé
2023-03-07 21:07       ` Philippe Mathieu-Daudé
2023-03-07 21:21         ` Jiaxun Yang
2023-03-07 22:14           ` Philippe Mathieu-Daudé

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