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[95.127.34.131]) by smtp.gmail.com with ESMTPSA id f2-20020a5d4dc2000000b002be5bdbe40csm12594530wru.27.2023.03.07.06.32.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Mar 2023 06:32:40 -0800 (PST) Message-ID: Date: Tue, 7 Mar 2023 15:32:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 2/2] hw/mips: Add MIPS virt board Content-Language: en-US To: Jiaxun Yang , qemu-devel@nongnu.org References: <20230304223803.55764-1-jiaxun.yang@flygoat.com> <20230304223803.55764-3-jiaxun.yang@flygoat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230304223803.55764-3-jiaxun.yang@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/3/23 23:38, Jiaxun Yang wrote: > MIPS virt board is design to utilize existing VirtIO infrastures > but also comptitable with MIPS's existing internal simulation tools. > > It includes virtio-pci, virtio-mmio, pcie gpex, flash rom, fw_cfg, > goldfish-rtc and MIPS CPS system. > > It should be able to cooperate with any MIPS CPU cores. > > Signed-off-by: Jiaxun Yang > --- > v1: > - Rename to virt board > - Convert BIOS flash to ROM > - Cleanups > v2: > - Fix fdt flash > - Remove UP variant > --- > MAINTAINERS | 7 + > configs/devices/mips-softmmu/common.mak | 1 + > docs/system/target-mips.rst | 22 + > hw/mips/Kconfig | 17 + > hw/mips/meson.build | 1 + > hw/mips/virt.c | 916 ++++++++++++++++++++++++ > 6 files changed, 964 insertions(+) > create mode 100644 hw/mips/virt.c > +static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) > +{ > + uint64_t regaddr; > + const MemMapEntry *memmap = virt_memmap; > + > + /* Move CM GCRs */ > + regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), Eh this is odd C... > + bl_gen_write_ulong(&p, regaddr, memmap[VIRT_CM].base); > + > + /* Move & enable GIC GCRs */ > + regaddr = cpu_mips_phys_to_kseg1(NULL, memmap[VIRT_CM].base + > + GCR_GIC_BASE_OFS), > + bl_gen_write_ulong(&p, regaddr, > + memmap[VIRT_GIC].base | GCR_GIC_BASE_GICEN_MSK); > + > + /* Move & enable CPC GCRs */ > + regaddr = cpu_mips_phys_to_kseg1(NULL, memmap[VIRT_CM].base + > + GCR_CPC_BASE_OFS), > + bl_gen_write_ulong(&p, regaddr, > + memmap[VIRT_CPC].base | GCR_CPC_BASE_CPCEN_MSK); > + > + /* > + * Setup argument registers to follow the UHI boot protocol: > + * > + * a0/$4 = -2 > + * a1/$5 = virtual address of FDT > + * a2/$6 = 0 > + * a3/$7 = 0 > + */ > + bl_gen_jump_kernel(&p, > + true, 0, true, (int32_t)-2, > + true, fdt_addr, true, 0, true, 0, > + kernel_entry); > +}